US2016148895A1PendingUtilityA1

Semiconductor device and manufacturing method thereof

Assignee: RENESAS ELECTRONICS CORPPriority: Jul 19, 2013Filed: Jan 21, 2016Published: May 26, 2016
Est. expiryJul 19, 2033(~7 yrs left)· nominal 20-yr term from priority
H10W 90/754H10W 90/734H10W 74/117H10W 74/00H10W 72/07554H10W 72/5525H10W 72/5522H10W 72/5449H10W 72/932H10W 72/926H10W 72/884H10W 72/547H10W 72/0198H10W 72/073H10W 90/701H10W 74/01H10W 72/075H10W 70/635H10W 70/465H10W 70/65H10W 70/04H10W 72/015H01L 2224/49171H01L 24/85H01L 2224/49433H01L 24/43H01L 23/49816H01L 23/49827H01L 21/56H01L 24/49
44
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A method for manufacturing a semiconductor device, includes providing a wiring substrate having a first surface and a second surface, the first surface being provided with a plurality of leads, after the providing of the wiring substrate, arranging a semiconductor chip with a main surface, a plurality of electrode pads formed at the main surface, and a back surface opposite to the main surface, over the first surface of the wiring substrate such that the back surface of the semiconductor chip is opposed to the first surface of the wiring substrate, after the arranging of the semiconductor chip, electrically coupling the electrode pads formed along three out of four sides of the main surface of the semiconductor chip to the leads disposed at the first surface of the wiring substrate via a plurality of metal wires, and after the electrically coupling of the electrode pads, forming a seal body over the first surface of the wiring substrate.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A method for manufacturing a semiconductor device, comprising:
 providing a wiring substrate having a first surface and a second surface opposite thereto, the first surface being formed in a rectangular shape and provided with a plurality of leads;   after the providing of the wiring substrate, arranging a semiconductor chip with a quadrilateral main surface, a plurality of electrode pads formed at the main surface, and a back surface opposite to the main surface, over the first surface of the wiring substrate such that the back surface of the semiconductor chip is opposed to the first surface of the wiring substrate;   after the arranging of the semiconductor chip, electrically coupling the electrode pads formed along three out of four sides of the main surface of the semiconductor chip to the leads disposed at the first surface of the wiring substrate via a plurality of metal wires; and   after the electrically coupling of the electrode pads, forming a seal body over the first surface of the wiring substrate by sealing the semiconductor chip and the metal wires with resin,   wherein the forming of the seal body comprises charging a resin for sealing from one side opposed to one of four sides of the main surface of the semiconductor chip not having the metal wires disposed thereat to thereby form the seal body.   
     
     
         2 . The method for manufacturing a semiconductor device according to  claim 1 , wherein the semiconductor chip includes a memory circuit and a logic circuit. 
     
     
         3 . The method for manufacturing a semiconductor device according to  claim 2 , wherein the metal wires disposed in parallel along a short side of the first surface of the wiring substrate are arranged at two respective opposed sides of the main surface of the semiconductor chip,
 wherein the leads are provided in a plurality of lines along the short side of the first surface outside the two respective opposed sides of the chip, and   wherein the metal wires are electrically coupled to the leads.   
     
     
         4 . The method for manufacturing a semiconductor device according to  claim 2 , wherein the metal wires are arranged at one side intersecting the two opposed sides of the main surface of the semiconductor chip,
 wherein the leads are arranged in one line outside the intersecting one side at the first surface of the wiring substrate, and   wherein the metal wires are electrically coupled to the leads.   
     
     
         5 . The method for manufacturing a semiconductor device according to  claim 1 , wherein the plurality of leads are provided in:
 a plurality of lines at the first surface of the wiring substrate along a short side of the first surface outside respective sides of any one of two pairs of the opposed sides of the main surface of the semiconductor chip; and   a line formed along a long side of the first surface, a distance between the short side of the first surface and the plurality of lines being greater than a distance between the long side of the first surface and the line formed along the long side of the first surface, and   wherein the metal wires are electrically coupled to the leads.

Join the waitlist — get patent alerts

Track US2016148895A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.