US2016148892A1PendingUtilityA1

Solder in cavity interconnection structures

Assignee: INTEL CORPPriority: Mar 23, 2011Filed: Jan 28, 2016Published: May 26, 2016
Est. expiryMar 23, 2031(~4.7 yrs left)· nominal 20-yr term from priority
H10W 90/724H10W 90/722H10W 72/07254H10W 72/07236H10W 72/07232H10W 72/07227H10W 72/01257H10W 72/01225H10W 72/01223H10W 72/856H10W 72/354H10W 72/325H10W 72/285H10W 72/283H10W 72/252H10W 72/242H10W 72/241H10W 72/073H10W 72/072H10W 72/30H10W 90/701H10W 74/127H10W 74/114H10W 74/15H10W 74/012H10W 72/20H05K 1/181H01L 2224/16238H01L 23/3121H01L 23/49816H01L 23/3142H01L 24/17H01L 2224/16227
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Claims

Abstract

The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A microelectronic device, comprising:
 a first substrate having a contact surface comprising a plurality of bond pads;   a dielectric structure disposed on the contact surface of the first substrate, wherein the first dielectric structure has a plurality of cavities extending therethrough to each of the plurality of first substrate bond pads, wherein the cavities of the plurality of cavities have a substantially frustoconical shape, and wherein an intercavity section of the first dielectric layer that is between two adjacent cavities of the plurality of cavities, comprises a first and a second surface that are substantially planar and are parallel to the contact surface of the first substrate;   a second substrate having a surface comprising a plurality of contact lands; and   solder interconnections between the plurality of first substrate bond pads and corresponding second substrate contact lands of the plurality of second substrate contact lands.   
     
     
         2 . The microelectronic device of  claim 1 , wherein the plurality of cavities are narrower at a first end that is closest to the contact surface of the first substrate and wider at a second end that is furthest from the contact surface of the first substrate. 
     
     
         3 . The microelectronic device of  claim 1 , further including an underfill material between the first substrate and the second substrate. 
     
     
         4 . The microelectronic device of  claim 1 , wherein the inter-cavity walls are deformable. 
     
     
         5 . The microelectronic device of  claim 1 , wherein a microelectronic die is operably coupled to the first substrate. 
     
     
         6 . The microelectronic device of  claim 1 , wherein the second substrate is a microelectronic device package.

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