Bond Pad Having Ruthenium Covering Passivation Sidewall

Abstract

A method of forming bond pads includes providing a substrate including an integrated circuit (IC) device formed thereon having an oxidizable uppermost metal interconnect layer which provides a plurality of bond pads that are coupled to circuit nodes on the IC device. The plurality of bond pads include a metal bond pad area. At least one passivation layer provides a trench including dielectric sidewalls above the metal bond pad area. A ruthenium (Ru) layer is deposited directly on the dielectric sidewalls and directly on the metal bond pad area, which removes the need for a barrier layer lining the dielectric sidewalls of the trench. The Ru layer is patterned to provide a bond pad surface for the plurality of bond pads.

What is claimed is: 
     
         1 . A device, comprising:
 a semiconductor substrate;   a metal layer formed above the semiconductor substrate;   a bond pad metal area formed above the metal layer and coupled to the metal layer using a via plug;   a passivation layer patterned with an opening exposing the bond pad metal area, the passivation layer forming a trench with the bond pad metal area, the trench having passivation sidewalls; and   a ruthenium (Ru) layer covering the passivation sidewalls and the bond pad metal area.   
     
     
         2 . The device of  claim 1 , wherein the Ru layer is formed directly on the passivation sidewalls and the bond pad metal area. 
     
     
         3 . The device of  claim 1 , further comprising:
 a barrier layer formed directly on the passivation sidewalls and the bond pad metal area, the barrier layer directly interfacing the bond pad metal area with the Ru layer.   
     
     
         4 . The device of  claim 1 , further comprising:
 a barrier layer formed directly on the passivation sidewalls and the bond pad metal area;   a nickel layer formed directly on the barrier layer and within the trench, wherein the Ru layer is positioned directly on the nickel layer.   
     
     
         5 . The device of  claim 1 , further comprising:
 a barrier layer formed directly on the passivation sidewalls and the bond pad metal area, the barrier layer interfacing the bond pad metal area with the Ru layer, the barrier layer includes a material selected from a group consisting of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), and combinations thereof.   
     
     
         6 . The device of  claim 1 , further comprising:
 a first transistor formed in the semiconductor substrate;   a second transistor formed in the semiconductor substrate, wherein the metal layer couples the first transistor to the second transistor.   
     
     
         7 . The device of  claim 1 , wherein the bond pad metal area and the Ru layer form a bond pad sized to receive a bond wire. 
     
     
         8 . The device of  claim 1 , wherein the Ru layer has a thickness greater than 0.2 um. 
     
     
         9 . The device of  claim 1 , wherein the passivation layer has a top surface above the trench and free of contact from the Ru layer. 
     
     
         10 . An integrated circuit, comprising:
 a substrate;   transistors formed on the substrate;   a metal layer formed above the substrate and interconnecting the transistors;   an bond pad metal area formed above the metal layer and coupled to the metal layer using a via plug;   a passivation layer patterned with an opening exposing the bond pad metal area, the passivation layer forming a trench with the bond pad metal area, the trench having passivation sidewalls; and   a ruthenium (Ru) layer covering the passivation sidewalls and the bond pad metal area.   
     
     
         11 . The integrated circuit of  claim 10 , wherein the Ru layer is formed directly on the passivation sidewalls and the bond pad metal area. 
     
     
         12 . The integrated circuit of  claim 10 , further comprising:
 a barrier layer formed directly on the passivation sidewalls and the bond pad metal area, the barrier layer directly interfacing the bond pad metal area with the Ru layer.   
     
     
         13 . The integrated circuit of  claim 10 , further comprising:
 a barrier layer formed directly on the passivation sidewalls and the bond pad metal area;   a nickel layer formed directly on the barrier layer and within the trench, wherein the Ru layer is positioned directly on the nickel layer.   
     
     
         14 . The integrated circuit of  claim 10 , wherein the bond pad metal area and the Ru layer form a bond pad sized to receive a bond wire. 
     
     
         15 . The integrated circuit of  claim 10 , the Ru layer has a thickness greater than 0.2 um. 
     
     
         16 . The integrated circuit of  claim 10 , wherein the passivation layer has a top surface above the trench and free of contact from the Ru layer. 
     
     
         17 . A method, comprising:
 patterning a passivation layer to define an opening exposing a bond pad metal area on a semiconductor wafer and to form a trench having passivation sidewalls surrounding the opening; and   forming a ruthenium (Ru) layer to cover the passivation sidewalls and the bond pad metal area of the trench.   
     
     
         18 . The method of  claim 17 , further comprising:
 removing the Ru layer on a top surface of the passivation layer while preserving the Ru layer covering the trench.   
     
     
         19 . The method of  claim 17 , wherein the forming the Ru layer includes:
 depositing a Ru material directly onto the passivation sidewalls and the bond pad metal area.   
     
     
         20 . The method of  claim 17 , further comprising:
 forming a barrier layer directly on the passivation sidewalls and the bond pad metal area, the barrier layer including a material selected from a group consisting of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), and combinations thereof,   wherein the forming the Ru layer includes depositing a Ru material directly onto the barrier layer.