Memory system with selective access to first and second memories

Abstract

A memory system includes a nonvolatile memory having a plurality of nonvolatile memory chips incorporated therein, a control circuit that controls the nonvolatile memory, an MPU that controls the control circuit, and an interface circuit that communicates with a host, all of which are mounted on a board of the memory system, and the memory system further includes a bus switch that switches connection of a signal line between the control circuit and the nonvolatile memory chips.

1 - 10 . (canceled) 
     
     
         11 . A memory device comprising:
 a first interface configured to receive a chip enable signal;   a first memory configured to be enabled by the chip enable signal received from the first interface;   a second memory configured to be enabled by the chip enable signal received from the first interface; and   a second interface configured to receive a first signal, the second interface is in between the first memory and the second memory; wherein   the chip enable signal selects a target memory, and the first signal determines whether the target memory is able to accept commands.   
     
     
         12 . The memory device according to  claim 11 , wherein the chip enable signal is shared by the first and second memory. 
     
     
         13 . The memory device according to  claim 11 , wherein
 the second interface transmits I 0  data and control signals, the second interface is connected to the first memory and second memory, and the second interface includes a first line that transmits the first signal.   
     
     
         14 . The memory device according to  claim 12 , wherein
 the first line includes one end connected to one of the first and second memory and the other end not connected to the first and second memory.   
     
     
         15 . The memory device according to  claim 11 , wherein the first memory and the second memory share a same pin. 
     
     
         16 . The memory device according to  claim 11 , wherein the first memory and the second memory share a same JO data bus through the second interface. 
     
     
         17 . The memory device according to  claim 11 , wherein the first memory is either one of a first NAND chip, a first group of NAND chips, or a first NAND package, and the second memory is either one of a second NAND chip, a second group of NAND chips, or a second NAND package. 
     
     
         18 . The memory device according to  claim 11 , wherein the first memory and second memory belong to a same channel. 
     
     
         19 . The memory device according to  claim 11 , wherein the target memory is appointed by an address that is transmitted through the second interface. 
     
     
         20 . A memory device comprising:
 a first interface configured to receive a first chip enable signal;   a second interface configured to receive a second chip enable signal;   a first memory configured to be enabled by the first chip enable signal received from the first interface;   a second memory configured to be enabled by the second chip enable signal received from the second interface; and   a third interface configured to receive a first signal, the third interface is in between the first memory and the second memory; wherein   the first and second chip enable signals select respectively the first and second memories as target memories, and   the first signal determines whether the selected target memory is able to accept commands.   
     
     
         21 . A memory device comprising:
 a first interface configured to output a first chip enable signal and a second chip enable signal;   a first memory configured to be enabled by the first chip enable signal;   a second memory configured to be enabled by the second chip enable signal; and   a second interface configured to receive a third signal, and the second interface connected to the first memory and to the second memory;   wherein:   the first and second chip enable signals select respectively the first and second memories as target memories, and   the third signal determines whether the selected target memory is able to accept commands based on the first and second chip enable signals.   
     
     
         22 . The memory device according to  claim 21 , wherein the first memory is a first group of memory chips and the second memory is a second group of memory chips. 
     
     
         23 . The memory device according to  claim 21 , wherein the first and second memories are part of a NAND memory package. 
     
     
         24 . The memory device according to  claim 22 , wherein the first and second groups of memory chips are part of a NAND memory package. 
     
     
         25 . The memory device according to  claim 22 , wherein the second interface is a bus switch. 
     
     
         26 . The memory device according to  claim 25 , wherein the third signal is a bus switch signal output from the bus switch. 
     
     
         27 . The memory device according to  claim 24 , wherein the second interface is a bus switch. 
     
     
         28 . The memory device according to  claim 27 , wherein the third signal is a bus switch signal output from the bus switch, and the bus switch is connected to each individual memory of the first and second groups of memories. 
     
     
         29 . The memory device according to  claim 24 , wherein the first group of memories is a first 8 stack chip in the NAND memory package and the second group of chips is a second 8 stack chip in the NAND memory package. 
     
     
         30 . The memory device according to  claim 29 , wherein the second interface is a bus switch. 
     
     
         31 . The memory device according to  claim 30 , wherein the third signal is a bus switch signal output from the bus switch, and the bus switch is connected to each individual memory of the first and second groups of memories.