Controlling average power limits of a processor

Abstract

In one embodiment, a processor includes at least one core to execute instructions, one or more thermal sensors associated with the at least one core, and a power controller coupled to the at least one core. The power controller has a control logic to receive temperature information regarding the processor and dynamically determine a maximum allowable average power limit based at least in part on the temperature information. The control logic may further maintain a static maximum base operating frequency of the processor regardless of a value of the temperature information. Other embodiments are described and claimed.

What is claimed is: 
     
         1 . A processor comprising:
 at least one core to execute instructions;   one or more thermal sensors associated with the at least one core; and   a power controller coupled to the at least one core, the power controller having a control logic to receive temperature information regarding the processor and dynamically determine a maximum allowable average power limit based at least in part on the temperature information, wherein the control logic is to maintain a static maximum base operating frequency of the processor regardless of a value of the temperature information.   
     
     
         2 . The processor of  claim 1 , wherein the maximum allowable average power limit comprises a thermal design power (TDP) value. 
     
     
         3 . The processor of  claim 2 , wherein when a temperature of the processor is less than a first threshold, the control logic is to dynamically determine the maximum allowable average power limit to be above the TDP value. 
     
     
         4 . The processor of  claim 3 , wherein when the temperature of the processor exceeds the first threshold, the control logic is to maintain the maximum allowable average power limit at the TDP value. 
     
     
         5 . The processor of  claim 2 , wherein the TDP value comprises a published TDP value for the processor. 
     
     
         6 . The processor of  claim 1 , wherein the control logic is to overwrite a specified maximum allowable average power limit stored in a configuration storage with the dynamically determined maximum allowable average power limit. 
     
     
         7 . The processor of  claim 6 , wherein the power controller further comprises a power budget logic to determine a power budget of the processor based at least in part on the dynamically determined maximum allowable average power limit, a previous energy budget and a previous energy consumption value. 
     
     
         8 . The processor of  claim 7 , wherein the control logic is to determine an operating frequency of the processor to be higher than the static maximum base operating frequency, based at least in part on the dynamically determined maximum allowable average power limit being above the specified maximum allowable average power limit. 
     
     
         9 . The processor of  claim 1 , wherein the control logic is to access an entry in a first table based on the temperature information and to obtain a power limit scaling value from the entry. 
     
     
         10 . The processor of  claim 9 , wherein the control logic is to dynamically determine the maximum allowable average power limit based on a specified maximum allowable average power limit and the power limit scaling value. 
     
     
         11 . The processor of  claim 1 , wherein the control logic is to access an entry in a first table based on the temperature information and to obtain an updated maximum allowable average power limit from the entry. 
     
     
         12 . A machine-readable medium having stored thereon data, which if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform a method comprising:
 receiving thermal information of a processor;   mapping the thermal information to a range of a plurality of ranges;   based on the range, determining a power limit scaling factor; and   adjusting a thermal design power (TDP) value of the processor based on the power limit scaling factor, the TDP value stored in a first storage of the processor.   
     
     
         13 . The machine-readable medium of  claim 12 , wherein the method further comprises determining a power budget for the processor using the adjusted TDP value. 
     
     
         14 . The machine-readable medium of  claim 13 , wherein the method further comprises determining at least one operating parameter for the processor based on the power budget. 
     
     
         15 . The machine-readable medium of  claim 12 , wherein the method further comprises:
 receiving a customer requested power limit of the processor;   if the customer requested power limit is less than the TDP value stored in the first storage, enforcing the customer requested power limit; and   if the customer requested power limit is greater than the TDP value stored in the first storage and a temperature of the processor is less than a first threshold, adjusting the TDP value to be above the TDP value stored in the first storage.   
     
     
         16 . The machine-readable medium of  claim 12 , wherein the adjusted TDP value comprises a relaxed TDP value higher than the TDP value, the TDP value a rated TDP value for the processor. 
     
     
         17 . A system comprising:
 a processor having a plurality of cores and a control logic, when a temperature of the processor is less than a threshold temperature, to dynamically update a thermal design power (TDP) value to a relaxed TDP value, the relaxed TDP value higher than the TDP value, wherein the processor is to execute a workload at a first power consumption level based on the relaxed TDP value when the temperature is less than the threshold temperature and to execute the workload at a second power consumption level based on the TDP value when the temperature is greater than the threshold temperature, the first power consumption level greater than the second power consumption level; and   a dynamic random access memory (DRAM) coupled to the processor.   
     
     
         18 . The system of  claim 17 , wherein the processor is to execute the workload at a static base operating frequency regardless of the temperature of the processor. 
     
     
         19 . The system of  claim 17 , wherein the processor further comprises a table including a plurality of entries to store a plurality of TDP values, the control logic to obtain the relaxed TDP value from one of the entries of the table based at least in part on the temperature of the processor. 
     
     
         20 . The system of  claim 17 , wherein the control logic is to determine a power budget for the processor based at least in part on the relaxed TDP value and to update at least one operating parameter of the processor based on the power budget.