System, method, and medium

Abstract

A system that includes circuitry configured to receive a plurality of pieces of data; store, for each of the plurality of pieces of data in a first memory area, a first identifier and associated node information identifying a node that processes associated piece of data; delete one of the first identifiers from the first memory area in a case that a number of first identifiers stored in the first memory area reaches a threshold; generate a second identifier based on deleted first identifier by applying a predetermined calculation on the deleted first identifier, the second identifier being shorter than the first identifier; store, in a second memory area, the second identifier and the associated node information; cause a node, associated with one of the first identifier and the second identifier stored in one of the first and second memory area, to process one of the plurality of pieces of data.

What is claimed is: 
     
         1 . A system comprising:
 circuitry configured to
 receive a plurality of pieces of data; 
 store, for each of the plurality of pieces of data in a first memory area, a first identifier and associated node information identifying a node that processes associated piece of data; 
 delete a first identifier, among the first identifiers, from the first memory area in a case that a number of first identifiers stored in the first memory area reaches a threshold; 
 generate a second identifier based on the deleted first identifier by applying a predetermined calculation on the deleted first identifier, the second identifier being shorter than the first identifier; 
 store, in a second memory area, the second identifier and the associated node information identifying the node that processes the piece of data corresponding to the second identifier; 
 cause a node associated with one of the first identifiers stored in the first memory area to process one of the plurality of pieces of data in a case that the one of the first identifiers corresponding to the one of the plurality of pieces of data is stored in the first memory area; and 
 cause the node associated with the second identifier stored in the second memory area to process the piece of data corresponding to the second identifier in a case that the second identifier is stored in the second memory area. 
   
     
     
         2 . The system of  claim 1 , wherein the circuitry is configured to:
 store, in the first memory area, load information indicating a load corresponding to each of the plurality of pieces of data; and   delete the first identifier from the first memory area based on the load information in a case that the number of first identifiers stored in the first memory area reaches the threshold.   
     
     
         3 . The system of  claim 2 , wherein
 the circuitry is configured to delete a plurality of first identifiers in ascending order of load indicated by the load information out of the first identifiers stored in the first memory area.   
     
     
         4 . The system of  claim 2 , wherein the circuitry is configured to:
 store the second identifier and the load information corresponding to the deleted first identifier into the second memory area;   select, in a case that the number of first identifiers stored in the first memory area is less than the threshold, a second identifier of a plurality of second identifiers stored in the second memory area based on the load information;   generate a first identifier corresponding to the selected second identifier; and   store the generated first identifier, node information corresponding to the selected second identifier and the load information corresponding to the selected second identifier to the first memory area.   
     
     
         5 . The system of  claim 4 , wherein
 the circuitry is configured to select a plurality of second identifiers in descending order of load indicated in the load information in a case that the number of first identifiers stored in the first memory area is less than the threshold.   
     
     
         6 . The system of  claim 4 , wherein the circuitry is configured to:
 select a plurality of second identifiers from the second memory area in descending order of load indicated in the load information of the first identifier associated with the second identifier when the number of first identifiers stored in the first memory area is less than the threshold; and   select a first identifier based on the load information out of the first identifiers associated with the selected second identifiers.   
     
     
         7 . The system of  claim 2 , wherein
 the circuitry is configured to reduce a load difference among multiple nodes by changing the first node information associated with a first identifier in the first memory area and the second node information associated with a second identifier in the second memory area.   
     
     
         8 . The system of  claim 1 , further comprising:
 a plurality of nodes each configured to perform processing corresponding to the plurality of pieces of data received by the circuitry.   
     
     
         9 . The system of  claim 2 , further comprising:
 a plurality of nodes each including the circuitry according to  claim 2 , wherein   each of the circuitry is configured to modify a node identifier corresponding to at least one of the first identifiers based on the load corresponding to the at least one of the first identifiers.   
     
     
         10 . The system of  claim 9 , further comprising:
 a management node configured to
 acquire, from each of the plurality of nodes, information of load to be executed in each of the plurality of nodes; and 
 reduce a load difference among the plurality of nodes by instructing each of the plurality of nodes to modify the node identifier based on the acquired information of load. 
   
     
     
         11 . The system of  claim 2 , wherein
 the system is a node that processes at least one of the plurality of pieces of the data.   
     
     
         12 . A method comprising:
 receiving a plurality of pieces of data;   storing, by circuitry, for each of the plurality of pieces of data in a first memory area, a first identifier and associated node information identifying a node that processes associated piece of data;   deleting, by the circuitry, a first identifier, among the first identifiers, from the first memory area in a case that a number of first identifiers stored in the first memory area reaches a threshold;   generating, by the circuitry, a second identifier based on the deleted first identifier by applying a predetermined calculation on the deleted first identifier, the second identifier being shorter than the first identifier;   storing, by the circuitry, in a second memory area, the second identifier and the associated node information identifying the node that processes the piece of data corresponding to the second identifier;   cause, by the circuitry, a node associated with one of the first identifiers stored in the first memory area to process one of the plurality of pieces of data in a case that the one of the first identifiers corresponding to the one of the plurality of pieces of data is stored in the first memory area; and   cause, by the circuitry, the node associated with the second identifier stored in the second memory area to process the piece of data corresponding to the second identifier in a case that the second identifier is stored in the second memory area.   
     
     
         13 . The method of  claim 12 , further comprising:
 storing, by the circuitry, in the first memory area, load information indicating a load corresponding to each of the plurality of pieces of data; and   deleting the first identifier from the first memory area based on the load information in a case that the number of first identifiers stored in the first memory area reaches the threshold.   
     
     
         14 . The method of  claim 13 , wherein
 the deleting the first identifier includes deleting, by the circuitry, a plurality of first identifiers in ascending order of load indicated by the load information out of the first identifiers stored in the first memory area.   
     
     
         15 . The method of  claim 13 , further comprising:
 storing, by the circuitry, the second identifier and the load information corresponding to the deleted first identifier into the second memory area;   selecting, by the circuitry, in a case that the number of first identifiers stored in the first memory area is less than the threshold, a second identifier of a plurality of second identifiers stored in the second memory area based on the load information;   generating, by the circuitry, a first identifier corresponding to the selected second identifier; and   storing, by the circuitry, the generated first identifier, node information corresponding to the selected second identifier and the load information corresponding to the selected second identifier to the first memory area.   
     
     
         16 . The method of  claim 15 , wherein
 the selecting the second identifier from the second memory area includes selecting a plurality of second identifiers in descending order of load indicated in the load information in a case that the number of first identifiers stored in the first memory area is less than the threshold.   
     
     
         17 . The method of  claim 15 , wherein the selecting the second identifier from the second memory area includes:
 selecting, by the circuitry, a plurality of second identifiers from the second memory area in descending order of load indicated in the load information of the first identifier associated with the second identifier, and   selecting, by the circuitry, a first identifier based on the load information out of the first identifiers associated with the selected second identifiers.   
     
     
         18 . The method of  claim 13 , further comprising:
 reducing, by the circuitry, a load difference among multiple nodes by changing the first node information associated with a first identifier in the first memory area and the second node information associated with a second identifier in the second memory area.   
     
     
         19 . A non-transitory computer readable medium storing therein a program that causes a computer to execute a process, the process comprising:
 receiving a plurality of pieces of data;   storing, for each of the plurality of pieces of data in a first memory area, a first identifier and associated node information identifying a node that processes associated piece of data;   deleting a first identifier, among the first identifiers, from the first memory area in a case that a number of first identifiers stored in the first memory area reaches a threshold;   generating a second identifier based on the deleted first identifier by applying a predetermined calculation on the deleted first identifier, the second identifier being shorter than the first identifier;   storing, in a second memory area, the second identifier and the associated node information identifying the node that processes the piece of data corresponding to the second identifier;   cause a node associated with one of the first identifiers stored in the first memory area to process one of the plurality of pieces of data in a case that the one of the first identifiers corresponding to the one of the plurality of pieces of data is stored in the first memory area; and   cause the node associated with the second identifier stored in the second memory area to process the piece of data corresponding to the second identifier in a case that the second identifier is stored in the second memory area.