Power mosfets with improved efficiency for multi-channel class d audio amplifiers and packaging therefor
Abstract
A stereo class-D audio system includes a first die including four monolithically integrated NMOS high-side devices and a second a second die including four monolithically integrated PMOS low-side devices. The audio system also includes a set of electrical contacts for connecting the high and low-side devices to components within the a stereo class-D audio system, the set of electrical contacts including at least one supply contact for connecting the drains of the high-side devices to a supply voltage (Vcc) and at least one ground contact for connecting the drains of the low-side devices to ground, the electrical contacts also including respective contacts for each source of the high and low-side devices allowing the source of each high-side device to be connected to the source of a respective low-side device to form two H-bridge circuits.
Claims
exact text as granted — not AI-modified1 . (canceled)
2 . A stereo class-D audio amplifier comprising:
a first conductive die pad having at least one supply contact to connect to a supply voltage; a second conductive die pad having at least one ground contact to connect to a ground reference voltage; and a plurality of half-bridge circuits, each respective half bridge circuit of the plurality of half-bridge circuits including a high-side vertical N-channel MOSFET formed on a first die and a low-side vertical P-channel MOSFET formed on a second die, an interconnection of the low-side vertical P-channel MOSFET and the high-side vertical N-channel MOSFET forming an output of the respective half-bridge circuit, a drain of the high-side vertical N-channel MOSFET of each of the plurality of half-bridge circuits being electrically connected to the first conductive die pad, and a drain of the low-side vertical P-channel MOSFET of each of the plurality of half-bridge circuits being electrically connected to the second conductive die pad.
3 . The stereo class-D audio amplifier of claim 2 wherein the high-side vertical N-channel MOSFET and the low-side vertical P-channel MOSFET of each of the plurality of half-bridge circuits is a DMOS MOSFET.
4 . The stereo class-D audio amplifier of claim 3 wherein the plurality of half-bridge circuits includes at least 4 half-bridge circuits.
5 . The stereo class-D audio amplifier of claim 4 wherein the stereo class-D audio amplifier is packaged in a single integrated circuit.
6 . The stereo class-D audio amplifier of claim 2 wherein each respective high-side vertical N-channel MOSFET and the corresponding low-side vertical P-channel MOSFET forms a complementary follower.
7 . The stereo class-D audio amplifier of claim 6 further comprising a plurality of break-before-make buffers corresponding to each of the plurality of high-side vertical N-channel MOSFETs.
8 . The stereo class-D amplifier of claim 7 wherein each respective break-before-make buffer is connected to a respective one of the plurality of high-side vertical N-channel MOSFETs and the corresponding low-side vertical P-channel MOSFETs.
9 . The stereo class-D audio amplifier of claim 2 wherein the first conductive die pad and the second conductive die pad have an H-shape.
10 . A stereo class-D audio amplifier comprising:
a plurality of high-side vertical power MOSFETs; a corresponding plurality of low-side vertical power MOSFETs corresponding to each high-side vertical power MOSFET of the plurality of high-side vertical power MOSFETs; and an interconnection between each respective high-side vertical power MOSFET and the corresponding low-side vertical power MOSFET forming a respective half-bridge output of the stereo class-D audio amplifier, each of the plurality of high-side vertical power MOSFETs being formed on a first die and each of the corresponding plurality of low-side vertical power MOSFETs being formed on a second die, a drain of each of the high-side vertical power MOSFETs being electrically connected by a backside of the first die to a first single die pad, and a drain of each of the low-side vertical power MOSFETs being electrically connected by a backside of the second die to a second single die pad.
11 . The stereo class-D audio amplifier of claim 10 wherein each respective high-side vertical power MOSFET and the corresponding low-side vertical power MOSFET forms a complementary follower.
12 . The stereo class-D audio amplifier of claim 11 wherein each low-side vertical power MOSFET of the corresponding plurality of low-side vertical power MOSFETs is a P-channel MOSFET.
13 . The stereo class-D audio amplifier of claim 11 wherein each high-side vertical power MOSFET of the plurality of high-side vertical power MOSFETs is an N-channel MOSFET.
14 . The stereo class-D audio amplifier of claim 10 wherein the plurality of high-side vertical power MOSFETs includes at least 4 MOSFETs and the corresponding plurality of low-side vertical power MOSFETs includes at least 4 MOSFETs.
15 . The stereo class-D audio amplifier of claim 14 wherein each low-side vertical power MOSFET of the corresponding plurality of low-side vertical power MOSFETs is a P-channel MOSFET and each high-side vertical power MOSFET of the plurality of high-side vertical power MOSFETs is an N-channel MOSFET.
16 . The stereo class-D audio amplifier of claim 10 wherein the stereo class-D audio amplifier is packaged in a single integrated circuit.
17 . The stereo class-D amplifier of claim 10 wherein the first single die pad is electrically connected to at least one power supply contact.
18 . The stereo class-D audio amplifier of claim 17 wherein the second single die pad is electrically connected to at least one ground contact.
19 . The stereo class-D audio amplifier of claim 10 wherein the first single die pad and the second single die pad have an H-shape.
20 . The stereo class-D audio amplifier of claim 10 wherein each of the plurality of high-side vertical power MOSFETs and each of the corresponding plurality of low-side vertical power MOSFETs is a DMOS MOSFET.
21 . The stereo class-D audio amplifier of claim 10 further comprising a plurality of break-before-make buffers corresponding to each of the plurality of high-side vertical power MOSFETs, each respective break-before-make buffer being connected to a respective one of the plurality of high-side vertical power MOSFETs and the corresponding low-side vertical power MOSFET.Join the waitlist — get patent alerts
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