Iii-v semiconductor devices with selective oxidation

Abstract

Embodiments of the present invention provide methods for fabricating a semiconductor device with selective oxidation. One method may include providing a semiconductor substrate including a stack of two semiconductor layers; depositing an insulating material on the semiconductor substrate; forming a set of fins; selectively oxidizing one of the semiconductor layers; forming a dummy gate structure and a set of spacers along the sides of the dummy gate structure; forming a source drain region adjacent to the dummy gate structure; removing the dummy gate structure; and releasing the selectively oxidized semiconductor layer.

What is claimed is: 
     
         1 . A method for fabricating a semiconductor device with selective oxidation, the method comprising:
 providing a semiconductor substrate comprising a stack of two crystalline semiconductor layers, wherein the stack of two crystalline semiconductor layers are disposed on a top surface of the semiconductor substrate;   depositing an insulating material on the semiconductor substrate;   etching one or more recesses into the insulating material to form a set of fins;   selectively oxidizing one of the two crystalline semiconductor layers;   forming a dummy gate structure and a set of spacers along sides of the dummy gate structure;   forming a source drain region adjacent to the dummy gate structure;   removing the dummy gate structure; and   releasing the selectively oxidized crystalline semiconductor layer.   
     
     
         2 . The method of  claim 1 , further comprising:
 forming a replacement gate structure between the set of spacers; and   depositing a high-K material around the replacement gate structure.   
     
     
         3 . The method of  claim 1 , wherein the stack of two crystalline semiconductor layers comprises a first layer configured to oxidize to an insulator and a second semiconductor layer configured to not oxidize to an insulator. 
     
     
         4 . The method of  claim 1 , wherein the step of selectively oxidizing one of the two crystalline semiconductor layers comprises exposing the semiconductor substrate in water vapor at a temperature that is greater than or equal to 350° C. and less than or equal to 550° C. 
     
     
         5 . The method of  claim 1 , wherein the source drain region adjacent to the dummy gate structure is formed using an ion implantation process or epitaxy. 
     
     
         6 . The method of  claim 1 , wherein releasing the selectively oxidized crystalline semiconductor layer is selective, at least in part, to a spacer layer, a channel layer, and a dielectric layer. 
     
     
         7 . The method of  claim 1 , wherein selectively oxidizing one of the two crystalline semiconductor layers occurs after providing the semiconductor substrate comprising the stack of two crystalline semiconductor layers. 
     
     
         8 . The method of  claim 1 , where the set of spacers are composed of: a nitride, an oxide, or an oxynitride. 
     
     
         9 . A semiconductor structure comprising:
 a stack of two crystalline semiconductor layers grown on a starting semiconductor substrate, wherein the stack of two crystalline semiconductor layers comprises a first layer and a second layer;   a plurality of fins patterned in the starting semiconductor substrate;   a gate structure and a set of spacers, wherein a portion of the gate structure and the set of spacers are disposed around the plurality of fins;   a source drain region formed adjacent to the gate structure; and   a high-K dielectric material disposed around the gate structure.   
     
     
         10 . The semiconductor structure of  claim 9 , wherein the starting semiconductor substrate comprises a layer of Ge, and wherein the layer of Ge has a thickness that is greater than or equal to 100 nm and less than or equal to 1 micrometer. 
     
     
         11 . The semiconductor structure of  claim 9 , wherein the first layer of the stack of two crystalline semiconductor layers is composed of a semiconducting material capable of being oxidized to a mechanically stable insulator. 
     
     
         12 . The semiconductor structure of  claim 9 , wherein the first layer has a thickness of 10 nm. 
     
     
         13 . The semiconductor structure of  claim 9 , wherein the second layer has a thickness of 10 nm. 
     
     
         14 . The semiconductor structure of  claim 9 , wherein the second layer is composed of one of: InGaAs and GaAs. 
     
     
         15 . The semiconductor structure of  claim 9 , further comprising more than one stack of two crystalline semiconductor layers grown on the starting semiconductor substrate. 
     
     
         16 . The semiconductor structure of  claim 9 , wherein a composition of the first layer is configured to be more readily oxidized than a composition of the second layer. 
     
     
         17 . The semiconductor structure of  claim 9 , wherein a lattice structure of the first layer is similar, at least in part, to a lattice structure of the second layer. 
     
     
         18 . The semiconductor structure of  claim 9 , wherein the high-K dielectric material is composed of: HfO, ZrO, or TiO. 
     
     
         19 . The semiconductor structure of  claim 9 , where the set of spacers are composed of: a nitride, an oxide, or an oxynitride.