Semiconductor device and method of manufacturing same

Abstract

To provide a semiconductor device having improved reliability. An element isolation region comprised mainly of silicon oxide is buried in a trench formed in a semiconductor substrate. The semiconductor substrate in an active region surrounded by the element isolation region has thereon a gate electrode for MISFET via a gate insulating film. The gate electrode partially extends over the element isolation region and the trench has a nitrided inner surface. Below the gate electrode, fluorine is introduced into the vicinity of a boundary between the element isolation region and a channel region of MISFET.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a semiconductor substrate;   an element isolation region buried in a trench formed in the semiconductor substrate and comprised mainly of silicon oxide;   a first gate electrode for first MISFET formed, via a first gate insulating film, over the semiconductor substrate in a first active region surrounded by the element isolation region; and   a first source/drain region for the first MISFET formed in the semiconductor substrate in the first active region,   wherein the trench in the semiconductor substrate has a nitrided inner surface,   wherein a portion of the first gate electrode extends over the element isolation region, and   wherein below the first gate electrode, fluorine is introduced into the vicinity of a boundary between the element isolation region and a channel region of the first MISFET.   
     
     
         2 . The semiconductor device according to  claim 1 ,
 wherein the first MISFET is a p channel type.   
     
     
         3 . The semiconductor device according to  claim 1 , further comprising:
 a second gate electrode for second MISFET formed, via a second gate insulating film, over the semiconductor substrate in a second active region surrounded by the element isolation region; and   a second source/drain region for the second MISFET formed in the semiconductor substrate in the second active region,   wherein a portion of the second gate electrode extends over the element isolation region, and   wherein below the second gate electrode, no fluorine is introduced into the vicinity of a boundary between the element isolation region and a channel region of the second MISFET.   
     
     
         4 . The semiconductor device according to  claim 3 ,
 wherein the first MISFET is a p channel type, and   wherein the second MISFET is an n channel type.   
     
     
         5 . The semiconductor device according to  claim 3 ,
 wherein the second gate insulating film is thicker than the first gate insulating film.   
     
     
         6 . A semiconductor device, comprising:
 a semiconductor substrate;   an element isolation region buried in a trench formed in the semiconductor substrate and comprised mainly of silicon oxide;   a first gate electrode for first MISFET formed, via a first gate insulating film, over the semiconductor substrate in a first active region surrounded by the element isolation region; and   a first source/drain region for the first MISFET formed in the semiconductor substrate in the first active region,   wherein a portion of the first gate electrode extends over the element isolation region,   wherein the trench in the semiconductor substrate has a nitride layer obtained by nitriding the inner surface of the trench, and   wherein below the first gate electrode, the nitride layer is not formed at a boundary between an upper portion of the semiconductor substrate in the first active region and an upper portion of the element isolation region.   
     
     
         7 . The semiconductor device according to  claim 6 ,
 wherein the first MISFET is a p channel type.   
     
     
         8 . The semiconductor device according to  claim 6 , further comprising:
 a second gate electrode for second MISFET formed, via a second gate insulating film, over the semiconductor substrate in a second active region surrounded by the element isolation region; and   a second source/drain region for the second MISFET formed in the semiconductor substrate in the second active region,   wherein a portion of the second gate electrode extends over the element isolation region, and   wherein the nitride layer is also formed at a boundary between an upper portion of the semiconductor substrate in the second active region and an upper portion of the element isolation region.   
     
     
         9 . The semiconductor device according to  claim 8 ,
 wherein the first MISFET is a p channel type, and   wherein the second MISFET is an n channel type.   
     
     
         10 . The semiconductor device according to  claim 8 ,
 wherein the second gate insulating film is thicker than the first gate insulating film.   
     
     
         11 . A method of manufacturing a semiconductor device, comprising the steps of:
 (a) providing a semiconductor substrate;   (b) forming a trench in the semiconductor substrate;   (c) nitriding an inner surface of the trench in the semiconductor substrate;   (d) after the step (c), forming an element isolation region comprised mainly of silicon oxide in the trench;   (e) ion-implanting fluorine in the vicinity of a boundary between the element isolation region and the semiconductor substrate in a first active region surrounded by the element isolation region;   (f) after the step (e), forming a first gate electrode for first MISFET over the semiconductor substrate in the first active region via a first gate insulating film; and   (g) forming a first source/drain region for the first MISFET in the semiconductor substrate in the first active region, wherein a portion of the first gate electrode extends over the element isolation region.   
     
     
         12 . The method of manufacturing a semiconductor device according to  claim 11 ,
 wherein below the first gate electrode, fluorine ion-implanted in the step (e) is present in the vicinity of a boundary between the element isolation region and a channel region of the first MISFET.   
     
     
         13 . The method of manufacturing a semiconductor device according to  claim 12 ,
 wherein the first MISFET is a p channel type.