Display device

Abstract

Provided is to secure a data-writing period to a source line and reduce the number of the IC chips used. N image data (e.g., three image data, RGB) are sequentially input to one input terminal. Three switches, three first memory elements, three transfer switches, three second memory elements, and three buffers are connected in parallel to the input terminal. The three switches are turned on respectively. RGB image data are held in the three respective first memory elements. In a selection period of a gate line of an (m−1)-th row, image data of an m-th row are written to the first memory elements. When the three transfer switches are turned on in a selection period of a gate line of an m-th row, the image data are transferred to and held in the second memory elements. Then, the image data are output to each source line through each buffer.

1 . (canceled) 
     
     
         2 . A semiconductor device comprising:
 first to twelfth transistors;   first to twelfth capacitors; and   first to sixth buffers,   wherein each of a first terminal of the first transistor, a first terminal of the second transistor and a first terminal of the third transistor is electrically connected to a first input terminal,   wherein each of a first terminal of the fourth transistor, a first terminal of the fifth transistor and a first terminal of the sixth transistor is electrically connected to a second input terminal,   wherein a second terminal of the first transistor, a second terminal of the second transistor, a second terminal of the third transistor, a second terminal of the fourth transistor, a second terminal of the fifth transistor and a second terminal of the sixth transistor are electrically connected to the first to sixth capacitors, respectively,   wherein a first terminal of the seventh transistor, a first terminal of the eighth transistor, a first terminal of the ninth transistor, a first terminal of the tenth transistor, a first terminal of the eleventh transistor and a first terminal of the twelfth transistor are electrically connected to the second terminal of the first transistor, the second terminal of the second transistor, the second terminal of the third transistor, the second terminal of the fourth transistor, the second terminal of the fifth transistor and the second terminal of the sixth transistor, respectively,   wherein a second terminal of the seventh transistor, a second terminal of the eighth transistor, a second terminal of the ninth transistor, a second terminal of the tenth transistor, a second terminal of the eleventh transistor and a second terminal of the twelfth transistor are electrically connected to the seventh to twelfth capacitors, respectively,   wherein the second terminal of the seventh transistor, the second terminal of the eighth transistor, the second terminal of the ninth transistor, the second terminal of the tenth transistor, the second terminal of the eleventh transistor and the second terminal of the twelfth transistor are electrically connected to an input terminal of the first buffer, an input terminal of the second buffer, an input terminal of the third buffer, an input terminal of the fourth buffer, an input terminal of the fifth buffer and an input terminal of the sixth buffer, respectively, and   wherein an output terminal of the first buffer, an output terminal of the second buffer, an output terminal of the third buffer, an output terminal of the fourth buffer, an output terminal of the fifth buffer and an output terminal of the sixth buffer are connected to first to sixth output terminals, respectively.   
     
     
         3 . The semiconductor device according to  claim 2 ,
 wherein the first and the fourth transistors are turned on or off by a first signal,   wherein the second and the fifth transistors are turned on or off by a second signal,   wherein the third and the sixth transistors are turned on or off by a third signal, and   wherein the seventh to twelfth transistors are turned on or off by a fourth signal.   
     
     
         4 . The semiconductor device according to  claim 2 ,
 wherein each of the first to twelfth transistor comprises an oxide semiconductor in a channel formation region, and comprises a gate insulating layer including a region where a proportion of oxygen is larger than a proportion of a stoichiometric composition.   
     
     
         5 . The semiconductor device according to  claim 2 ,
 wherein each of the first to twelfth transistor comprises:   a first insulating layer;   an oxide semiconductor layer over the first insulating layer;   a gate insulating layer including a region where a proportion of oxygen is larger than a proportion of a stoichiometric composition, over the oxide semiconductor layer;   a gate electrode over the gate insulating layer;   a second insulating layer in contact with a side surface of the gate electrode;   an electrode in contact with the oxide semiconductor layer;   a third insulating layer over the gate electrode and the electrode; and   a wiring in contact with the electrode, over the third insulating layer.   
     
     
         6 . A semiconductor device comprising:
 first to twenty-fourth transistors; and   first to twelfth capacitors,   wherein each of a first terminal of the first transistor, a first terminal of the second transistor and a first terminal of the third transistor is electrically connected to a first input terminal,   wherein each of a first terminal of the fourth transistor, a first terminal of the fifth transistor and a first terminal of the sixth transistor is electrically connected to a second input terminal,   wherein a second terminal of the first transistor, a second terminal of the second transistor, a second terminal of the third transistor, a second terminal of the fourth transistor, a second terminal of the fifth transistor and a second terminal of the sixth transistor are electrically connected to the first to sixth capacitors, respectively,   wherein a first terminal of the seventh transistor, a first terminal of the eighth transistor, a first terminal of the ninth transistor, a first terminal of the tenth transistor, a first terminal of the eleventh transistor and a first terminal of the twelfth transistor are electrically connected to the second terminal of the first transistor, the second terminal of the second transistor, the second terminal of the third transistor, the second terminal of the fourth transistor, the second terminal of the fifth transistor and the second terminal of the sixth transistor, respectively,   wherein a second terminal of the seventh transistor, a second terminal of the eighth transistor, a second terminal of the ninth transistor, a second terminal of the tenth transistor, a second terminal of the eleventh transistor and a second terminal of the twelfth transistor are electrically connected to the seventh to twelfth capacitors, respectively,   wherein the second terminal of the seventh transistor, the second terminal of the eighth transistor, the second terminal of the ninth transistor, the second terminal of the tenth transistor, the second terminal of the eleventh transistor and the second terminal of the twelfth transistor are connected to a gate of the thirteenth transistor, a gate of the fourteenth transistor, a gate of the fifteenth transistor, a gate of the sixteenth transistor, a gate of the seventeenth transistor and a gate of the eighteenth transistor, respectively,   wherein a first terminal of the thirteenth transistor, a first terminal of the fourteenth transistor, a first terminal of the fifteenth transistor, a first terminal of the sixteenth transistor, a first terminal of the seventeenth transistor and a first terminal of the eighteenth transistor are connected to a first terminal of the nineteenth transistor, a first terminal of the twentieth transistor, a first terminal of the twenty-first transistor, a first terminal of the twenty-second transistor, a first terminal of the twenty-third transistor and a first terminal of the twenty-fourth transistor, respectively,   wherein the first terminal of the thirteenth transistor, the first terminal of the fourteenth transistor, the first terminal of the fifteenth transistor, the first terminal of the sixteenth transistor, the first terminal of the seventeenth transistor and the first terminal of the eighteenth transistor are connected to first to sixth output terminals, respectively, and   wherein each of a gate of the nineteenth transistor, a gate of the twentieth transistor, a gate of the twenty-first transistor, a gate of the twenty-second transistor, a gate of the twenty-third transistor and a gate of the twenty-fourth transistor is electrically connected to a bias terminal.   
     
     
         7 . The semiconductor device according to  claim 6 ,
 wherein the first and the fourth transistors are turned on or off by a first signal,   wherein the second and the fifth transistors are turned on or off by a second signal,   wherein the third and the sixth transistors are turned on or off by a third signal, and   wherein the seventh to twelfth transistors are turned on or off by a fourth signal.   
     
     
         8 . The semiconductor device according to  claim 6 ,
 wherein each of the first to twenty-fourth transistor comprises an oxide semiconductor in a channel formation region, and comprises a gate insulating layer including a region where a proportion of oxygen is larger than a proportion of a stoichiometric composition.   
     
     
         9 . The semiconductor device according to  claim 6 ,
 wherein each of the first to twenty-fourth transistor comprises:   a first insulating layer;   an oxide semiconductor layer over the first insulating layer;   a gate insulating layer including a region where a proportion of oxygen is larger than a proportion of a stoichiometric composition, over the oxide semiconductor layer;   a gate electrode over the gate insulating layer;   a second insulating layer in contact with a side surface of the gate electrode;   an electrode in contact with the oxide semiconductor layer;   a third insulating layer over the gate electrode and the electrode; and   a wiring in contact with the electrode, over the third insulating layer.