Threshold voltage adjustment in metal oxide semiconductor field effect transistor with silicon oxynitride polysilicon gate stack on fully depleted silicon-on-insulator

Abstract

A fully depleted silicon-on-insulator MOSFET transistor with reduced variation in threshold voltage. The substrate of the transistor is doped to form a ground plane below a buried oxide layer. A lightly doped channel is formed over the buried oxide layer. A gate dielectric of Silicon Oxynitride is formed over the channel, and a polysilicon gate is formed over the gate dielectric. The polysilicon gate is doped to have a work function not greater 4.2 electron volts for a p-type doped channel (for an n-channel MOSFET), and not less than 5.0 electron volts for an n-type doped channel (for a p-channel MOSFET). The thickness of the buried oxide layer and the channel need not be greater than 20 nanometers and 10 nanometers, respectively.

What is claimed is: 
     
         1 . A method, comprising:
 doping a silicon substrate to form a ground plane;   forming a buried oxide layer in the silicon substrate;   forming a p-type doped silicon channel on the buried oxide layer;   forming a first source/drain region in the silicon channel;   forming a second source/drain region in the silicon channel;   forming a dielectric layer on the silicon channel; and   forming a polysilicon gate on the dielectric layer such that a work function of the polysilicon gate is not greater than 4.2 eV.   
     
     
         2 . The method of  claim 1 ,
 wherein the silicon channel is formed to have a thickness not greater than 10 nm, and   wherein the buried oxide layer is formed to have a thickness not greater than 20 nm.   
     
     
         3 . The method of  claim 1 , wherein the silicon substrate is doped such that the doped ground plane has a doping concentration not less than 5×10 18 cm −3 . 
     
     
         4 . The method of  claim 1 ,
 wherein the silicon channel is formed to have a doping concentration not greater than 5×10 17 cm −3 , and   wherein the dielectric layer is formed to have a thickness in a range of 1.5 nm to 2.5 nm.   
     
     
         5 . The method of  claim 1 , wherein the dielectric layer formed on the silicon channel is selected from the group consisting of silicon dioxide, nitride silicon oxide, and silicon nitride. 
     
     
         6 . A method, comprising:
 doping a silicon substrate to form a ground plane;   forming a buried oxide layer in the silicon substrate;   forming an n-type doped silicon channel on the buried oxide layer;   forming a first source/drain region in the silicon channel;   forming a second source/drain region in the silicon channel;   forming a dielectric layer on the silicon channel; and   forming a polysilicon gate on the dielectric layer such that a work function of the polysilicon gate is not less than 5.0 eV.   
     
     
         7 . The method of  claim 6 ,
 wherein the silicon channel is formed to have a thickness not greater than 10 nm, and   wherein the buried oxide layer is formed to have a thickness not greater than 20 nm.   
     
     
         8 . The method of  claim 6 , wherein the silicon substrate is doped such that the doped ground plane has a doping concentration not less than 5×10 18 cm −3 . 
     
     
         9 . The method of  claim 6 ,
 wherein the silicon channel is formed to have a doping concentration not greater than 5×10 17 cm −3 , and   wherein the dielectric layer is formed to have a thickness in a range of 1.5 nm to 2.5 nm.   
     
     
         10 . The method of  claim 6 , wherein the dielectric layer formed on the silicon channel is selected from the group consisting of silicon dioxide, nitride silicon oxide, and silicon nitride. 
     
     
         11 . A method, comprising:
 doping a silicon substrate to form a ground plane;   forming a buried oxide layer in the silicon substrate;   forming a p-type or an n-type doped silicon channel on the buried oxide layer;   forming a first source/drain region in the silicon channel;   forming a second source/drain region in the silicon channel;   forming a dielectric layer on the silicon channel; and   forming a polysilicon gate on the dielectric layer such that a work function of the polysilicon gate is not greater than a first work function level when the silicon channel is doped the p-type, and is not less than a second work function level when the silicon channel is doped the n-type,   wherein the second work function level is higher than the first work function level, and   wherein the polysilicon gate is formed such that the work function of the polysilicon gate is not in between the first work function level and the second work function level.   
     
     
         12 . The method of  claim 11 , wherein the first work function level is 4.2 eV and the second work function level is 5.0 eV. 
     
     
         13 . The method of  claim 11 ,
 wherein the silicon channel is formed to have a thickness not greater than 10 nm, and   wherein the buried oxide layer is formed to have a thickness not greater than 20 nm.   
     
     
         14 . The method of  claim 11 , wherein the silicon substrate is doped such that the doped ground plane has a doping concentration not less than 5×10 18 cm −3 . 
     
     
         15 . The method of  claim 11 ,
 wherein the silicon channel is formed to have a doping concentration not greater than 5×10 17 cm −3 , and   wherein the dielectric layer is formed to have a thickness in a range of 1.5 nm to 2.5 nm.   
     
     
         16 . The method of  claim 11 , wherein the dielectric layer formed on the silicon channel is selected from the group consisting of silicon dioxide, nitride silicon oxide, and silicon nitride.