Alternative gate dielectric films for silicon germanium and germanium channel materials

Abstract

Embodiments of the present invention provide a high-K dielectric film for use with silicon germanium (SiGe) or germanium channel materials, and methods of fabrication. As a first step of this process, an interfacial layer (IL) is formed on the semiconductor substrate providing reduced interface trap density. However, an ultra-thin layer is used as a barrier film to avoid germanium diffusion in high-k film and oxygen diffusion from the high-k film to the interfacial layer (IL), therefore, dielectric films such as aluminum oxide (Al 2 O 3 ), zirconium oxide, or lanthanum oxide (La 2 O 3 ) may be used. In addition, these films can provide high thermal budget. A second dielectric layer is then deposited on the first dielectric layer. The second dielectric layer is a high-k dielectric layer, providing a reduced effective oxide thickness (EOT), resulting in improved device performance.

What is claimed is: 
     
         1 .- 12 . (canceled) 
     
     
         13 . A semiconductor structure comprising:
 a silicon germanium substrate comprising an oxidized top surface;   a first dielectric layer disposed on the oxidized top surface of the silicon germanium substrate; and   a second dielectric layer disposed on the first dielectric layer.   
     
     
         14 . The semiconductor structure of  claim 13 , wherein the first dielectric layer comprises aluminum oxide and lanthanum oxide. 
     
     
         15 . The semiconductor structure of  claim 14 , wherein the second dielectric layer comprises titanium oxide. 
     
     
         16 . The semiconductor structure of  claim 14 , wherein the second dielectric layer comprises lanthanum oxide. 
     
     
         17 . The semiconductor structure of  claim 14 , wherein the second dielectric layer comprises zirconium oxide. 
     
     
         18 . A semiconductor structure comprising:
 a semiconductor substrate;   a transistor gate disposed on the semiconductor substrate;   a gate dielectric disposed between the semiconductor substrate and the transistor gate, wherein the gate dielectric comprises an oxidized surface region of the semiconductor substrate, an aluminum oxide layer disposed on the oxidized surface region, and a high-K dielectric layer disposed on the aluminum oxide layer.   
     
     
         19 . The semiconductor structure of  claim 18 , wherein the high-K dielectric layer comprises a titanium oxide layer. 
     
     
         20 . The semiconductor structure of  claim 18 , wherein the high-K dielectric layer comprises zirconium oxide. 
     
     
         21 . A semiconductor structure comprising:
 a semiconductor substrate comprising an oxidized top surface;   a first dielectric layer disposed on the oxidized top surface of the semiconductor substrate; and   a second dielectric layer disposed on the first dielectric layer.   
     
     
         22 . The semiconductor structure of  claim 21 , wherein the first dielectric layer comprises aluminum oxide and lanthanum oxide. 
     
     
         23 . The semiconductor structure of  claim 22 , wherein the second dielectric layer comprises titanium oxide. 
     
     
         24 . The semiconductor structure of  claim 22 , wherein the second dielectric layer comprises lanthanum oxide. 
     
     
         25 . The semiconductor structure of  claim 22 , wherein the second dielectric layer comprises zirconium oxide. 
     
     
         26 . The semiconductor structure of  claim 13 , wherein the oxidized top surface has a thickness ranging from about 2 angstroms to about 5 angstroms. 
     
     
         27 . The semiconductor structure of  claim 18 , wherein the oxidized surface region has a thickness ranging from about 2 angstroms to about 5 angstroms. 
     
     
         28 . The semiconductor structure of  claim 21 , wherein the oxidized top surface has a thickness ranging from about 2 angstroms to about 5 angstroms.