Offset interposers for large-bottom packages and large-die package-on-package structures

Abstract

An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

What is claimed is: 
     
         1 . A package-on-package (POP) structure comprising:
 a processor device disposed within a first package substrate;   
       a land side ball grid array (BGA) comprising a plurality of land side electrical interconnect structures, wherein the land side BGA is electrically and mechanically coupled to the first package substrate; 
       an interposer electrically and mechanically coupled to the land side BGA, wherein the interposer comprises: 
       a land side, wherein a first land side pad and a second land side pad are disposed on the land side of the interposer and are adjacent to each other, and wherein the first land side pad is coupled to a first electrical interconnect structure of the BGA, and wherein the second land side pad is coupled to a second electrical interconnect structure of the BGA; and 
       a package-on-package (POP) side wherein a first POP side pad and a second POP side pad are disposed on the POP side of the interposer and are adjacent to each other, wherein the first land side pad is electrically coupled with the first POP side pad through the interposer, and wherein the second land side pad and the second POP side pad are electrically coupled to each other through the interposer, and wherein a center to center spacing between the first and second land side pads is smaller than a center to center spacing between the first and second POP-side pads; 
       a POP side BGA comprising a plurality of POP electrical interconnect structures, wherein the first POP side land is coupled with a first POP electrical interconnect structure, and wherein the second POP land is coupled with a second POP electrical interconnect structure; 
       a second package substrate comprising a POP substrate that is electrically coupled with the POP side BGA; and 
       a memory device electrically coupled to the POP substrate, wherein the memory device is electrically coupled to the interposer through the POP substrate. 
     
     
         2 . The structure of  claim 1  wherein the first land side pad is electrically coupled to the first POP side pad by direct contact with a via interconnect structure. 
     
     
         3 . The structure of  claim 1  wherein the center to center spacing between the first land side pad and the second land side pad does not overlap the spacing between the first POP side pad and the second POP side pad. 
     
     
         4 . The structure of  claim 1  wherein the center to center spacing between the first land side pad and the second land side pad overlaps the spacing between the first POP side pad and the second POP side pad. 
     
     
         5 . The structure of  claim 1  wherein the first and second land side pads are part of an array of land side pads that are all configures at a first pitch, and wherein the first and second POP side pads are part of an array of POP side pads that are all configured at a second pitch, wherein the first pitch is larger than the second pitch. 
     
     
         6 . The structure of  claim 1  wherein the first and second land side pads are part of an array of land side pads that are all configures at a first pitch, and wherein the first and second POP side pads are part of an array of POP side pads that are all configured at a second pitch, wherein the first pitch is larger than the second pitch. 
     
     
         7 . The structure of  claim 1  wherein the memory device is electrically coupled to the POP substrate by one of a wire bond connection or a flip chip connection. 
     
     
         8 . A method of forming an assembly, comprising: 
       forming an interposer, wherein the interposer is capable of electrically and mechanically coupling to a land side BGA and a POP side BGA, wherein forming the interposer comprises: forming a land side, wherein a first land side pad and a second land side pad are disposed on the land side of the interposer and are adjacent to each other, and wherein the first land side pad is coupled to a first electrical interconnect structure of the land side BGA, and wherein the second land side pad is coupled to a second electrical interconnect structure of the land side BGA; and forming a package-on-package (POP) side, wherein a first POP side pad and a second POP side pad are disposed on the POP side of the interposer and are adjacent to each other, wherein the first land side pad is electrically coupled with the first POP side pad through the interposer, and wherein the second land side pad and the second POP side pad are electrically coupled to each other through the interposer, and wherein a center to center spacing between the first and second land side pads is smaller than a center to center spacing between the first and second POP-side pads. 
     
     
         9 . The method of  claim 8  further comprising electrically coupling a POP side BGA to the POP side of the interposer, wherein the POP side BGA comprises a plurality of POP electrical interconnect structures, wherein the first POP side land is coupled with a first POP electrical interconnect structure, and wherein the second POP land is coupled with a second POP electrical interconnect structure. 
     
     
         10 . The method of  claim 8  further comprising electrically coupling a POP substrate with the POP side BGA. 
     
     
         11 . The method of  claim 10  further comprising electrically coupling a memory device to the POP substrate, wherein the memory device is electrically coupled to the interposer through the POP substrate. 
     
     
         12 . The method of  claim 1  further comprising electrically coupling a land side BGA to the land side of the interposer, wherein a processor device is electrically coupled to the land side BGA. 
     
     
         13 . The method of  claim 12  further comprising wherein the processor device is disposed within a first package, and the memory device is disposed within a second package. 
     
     
         14 . The method of  claim 9  further comprising wherein the first land side pad is electrically coupled to the first POP side pad by direct contact with a via interconnect structure. 
     
     
         15 . The method of  claim 9  further comprising wherein the center to center spacing between the first land side pad and the second land side pad does not overlap the spacing between the first POP side pad and the second POP side pad. 
     
     
         16 . The method of  claim 9  further comprising wherein the center to center spacing between the first land side pad and the second land side pad overlaps the spacing between the first POP side pad and the second POP side pad. 
     
     
         17 . The method of  claim 9  further comprising wherein the first and second land side pads are part of an array of land side pads that are all configures at a first pitch, and wherein the first and second POP side pads are part of an array of POP side pads that are all configured at a second pitch, wherein the first pitch is larger than the second pitch. 
     
     
         18 . The method of  claim 9  further comprising wherein the first and second land side pads are part of an array of land side pads that are all configures at a first pitch, and wherein the first and second POP side pads are part of an array of POP side pads that are all configured at a second pitch, wherein the first pitch is larger than the second pitch. 
     
     
         19 . The method of  claim 11  further comprising wherein the memory device is electrically coupled to the POP substrate by one of a wire bond connection or a flip chip connection.