Hybrid orientation fin field effect transistor and planar field effect transistor

Abstract

A substrate including a handle substrate, a lower insulator layer, a buried semiconductor layer, an upper insulator layer, and a top semiconductor layer is provided. Semiconductor fins can be formed by patterning a portion of the buried semiconductor layer after removal of the upper insulator layer and the top semiconductor layer in a fin region, while a planar device region is protected by an etch mask. A disposable fill material portion is formed in the fin region, and a shallow trench isolation structure can be formed in the planar device region. The disposable fill material portion is removed, and gate stacks for a planar field effect transistor and a fin field effect transistor can be simultaneously formed. Alternately, disposable gate structures and a planarization dielectric layer can be formed, and replacement gate stacks can be subsequently formed.

1 . A semiconductor structure comprising:
 a fin field effect transistor located on a first portion a lower insulator layer, said fin field effect transistor comprising at least one semiconductor fin and a first gate stack, wherein each of said at least one semiconductor fin comprises a fin source region, a fin drain region, and a fin body region, and said first gate stack comprises a first gate dielectric and a first gate electrode and straddles each of said at least one semiconductor fin;   a planar field effect transistor located on a stack, from bottom to top, of a second portion of said lower insulator layer, a buried semiconductor layer, and an upper insulator layer, said planar field effect transistor comprising a top semiconductor portion and a second gate stack, wherein said top semiconductor portion comprises a planar source region, a planar drain region, and a planar body region, and said second gate stack comprises a second gate dielectric and a second gate electrode; and   a planarization dielectric layer having a planar top surface, wherein a top surface of said first gate electrode and a top surface of said second gate electrode are coplanar with said planar top surface.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein said first and second gate dielectrics have a same composition and a same thickness, and said first and second gate electrodes comprise a same conductive material. 
     
     
         3 . The semiconductor structure of  claim 1 , wherein each of said first gate dielectric and said second gate dielectric is a U-shaped gate dielectric having a topmost surface that is coplanar with said planar top surface. 
     
     
         4 . The semiconductor structure of  claim 1 , wherein each of said at least one semiconductor fin has a vertical dimension between a bottommost surface and a topmost surface that is substantially the same as a thickness of said buried semiconductor layer. 
     
     
         5 . The semiconductor structure of  claim 1 , wherein said buried semiconductor layer and each of said at least one semiconductor fin have a same crystal structure and a same set of spatial directions for each of three independent crystallographic orientations. 
     
     
         6 . The semiconductor structure of  claim 1 , wherein said top semiconductor portion comprises a different semiconductor material than said buried semiconductor layer. 
     
     
         7 . The semiconductor structure of  claim 1 , wherein a first set of spatial directions for three independent crystallographic orientations of a single crystalline structure of said at least one semiconductor fin is rotated relative to a second set of spatial directions for three independent crystallographic orientations of a single crystalline structure of said top semiconductor portion. 
     
     
         8 . The semiconductor structure of  claim 1 , wherein said fin field effect transistor further comprises a raised fin source region epitaxially aligned to each fin source region in said at least one semiconductor fin and a raised fin drain region epitaxially aligned to each fin drain region in said at least one semiconductor fin, and said planar field effect transistor further comprises a raised source region in contact with said planar source region and a raised drain region in contact with said planar drain region, and said raised fin source region, said raised fin drain region, said raised source region, and said raised drain region comprise a same semiconductor material. 
     
     
         9 . The semiconductor structure of  claim 1 , further comprising:
 a first gate spacer laterally surrounding said first gate stack;   a second gate spacer laterally surrounding said second gate stack; and   a dielectric spacer contacting substantially vertical sidewalls of said buried semiconductor layer and said upper insulator layer and contacting a top surface of said lower insulator layer, wherein said first gate spacer, said second gate spacer, and said dielectric spacer comprise a same dielectric material and have a same lateral width at each bottom portion thereof.   
     
     
         10 - 18 . (canceled) 
     
     
         19 . A method of forming a semiconductor structure comprising:
 masking a region of a substrate including a stack, from bottom to top, of a handle substrate, a lower insulator layer, a buried semiconductor layer, an upper insulator layer, and a top semiconductor layer, while removing portions of said top semiconductor layer and said upper insulator layer in another region of said substrate;   forming at least one semiconductor fin by patterning said buried semiconductor layer within said another region;   forming a disposable fill material portion over said at least semiconductor fin in said another region;   forming a shallow trench isolation structure laterally surrounding a portion of said top semiconductor layer in said region; and   simultaneously forming a first gate stack over said at least one semiconductor fin and a second gate stack over said portion of said top semiconductor layer.   
     
     
         20 . The method of  claim 19 , wherein said masking of said region of said substrate comprises:
 forming a masking material layer as a blanket layer over said substrate; and   patterning said masking material layer to remove a portion of said masking layer from said another region while a portion of said masking material layer masks said region.   
     
     
         21 . The method of  claim 20 , wherein said removing of said portions of said top semiconductor layer and said upper insulator layer comprises etching said portions of said top semiconductor layer and said upper insulator layer employing said portion of said masking material layer as an etch mask and employing said buried semiconductor layer as an etch stop layer. 
     
     
         22 . The method of  claim 20 , wherein said forming of said disposable fill material portion comprises:
 depositing a disposable fill material over said at least one semiconductor fin and said portion of said masking material layer; and   planarizing said disposable fill material by removing said disposable fill material from above a plane of a top surface of said portion of said masking material layer.   
     
     
         23 . The method of  claim 20 , wherein said forming of said shallow trench isolation structure comprises:
 etching a shallow trench extending from a top surface of said portion of said masking material layer at least to a top surface of said upper insulator layer;   depositing a dielectric material within said shallow trench;   planarizing said dielectric material employing said portion of said masking material layer as a stopping layer; and   recessing said dielectric material below a top surface of said portion of said masking material layer.   
     
     
         24 . The method of  claim 20 , further comprising forming:
 a raised fin source region epitaxially aligned to each fin source region in said at least one semiconductor fin;   a raised fin drain region epitaxially aligned to each fin drain region in said at least one semiconductor fin;   a raised source region in contact with said planar source region; and   a raised drain region in contact with said planar drain region.   
     
     
         25 . The method of  claim 19 , further comprising simultaneously forming:
 a first gate spacer laterally surrounding said first gate stack;   a second gate spacer laterally surrounding said second gate stack; and   a dielectric spacer contacting substantially vertical sidewalls of said buried semiconductor layer and said upper insulator layer and contacting a top surface of said lower insulator layer, wherein said first gate spacer, said second gate spacer, and said dielectric spacer comprise a same dielectric material and have a same lateral width at each bottom portion thereof.   
     
     
         26 . The method of  claim 19 , further comprising forming a contact level dielectric layer over said first gate stack, said second gate stack and said lower insulator layer. 
     
     
         27 . The method of claim of  claim 26 , further comprising forming a contact via contact structure extending through the contact level dielectric layer and in contact with said buried semiconductor layer. 
     
     
         28 . The method of  claim 19 , wherein said forming said first gate stack and said second gate stack comprises:
 depositing a stack of a gate dielectric layer and a gate electrode layer over said top semiconductor layer, said shallow trench isolation structure, said at least one semiconductor fin and said buried semiconductor layer; and   patterning said stack of said gate dielectric layer and said gate electrode layer.   
     
     
         29 . The method of  claim 1 , wherein said planarization dielectric layer has a bottom surface contacting a top surface of said lower insulator layer.