Memory devices capable of reducing lateral movement of charges

Abstract

Memory devices are provided, the memory devices include a tunneling insulating layer disposed on a substrate, a charge storage layer disposed on the tunneling insulating layer, a blocking insulating layer disposed on the charge storage layer and a control gate electrode disposed on the blocking insulating layer. The control gate electrode may have an edge portion spaced farther apart from the blocking insulating layer than a central portion of the control gate electrode to concentrate charge density distribution on a central portion of a memory cell.

1 - 10 . (canceled) 
     
     
         11 . A memory device, comprising:
 a tunneling insulating layer on an active region;   a charge storage layer on the tunneling insulating layer;   a blocking insulating layer on the charge storage layer; and   a control gate electrode on the blocking insulating layer,   wherein the control gate electrode has an edge portion spaced farther apart from the blocking insulating layer than a central portion of the control gate electrode, and   wherein a surface of the control gate electrode, which faces the blocking insulating layer, has a central portion with a pointed inverted triangular sectional structure.   
     
     
         12 . The device of  claim 11 , wherein the edge portion of the control gate electrode has a thickness equal to, or smaller than, that of the central portion thereof, and
 the edge portion of the control gate electrode tapers outward towards a sidewall of the memory device and away from the blocking insulating layer.   
     
     
         13 . The device of  claim 11 , further comprising:
 at least two of the control gate electrodes; and   a bottom spacer between the at least two control gate electrodes, wherein the bottom spacer fills a region between the edge portion of the at least two control gate electrodes and the blocking insulating layer.   
     
     
         14 . The device of  claim 11 , further comprising:
 a gate dielectric material in the central portion of the memory cell corresponding to the central portion of the control gate electrode, wherein the gate dielectric material is thinner than that in an edge portion of the memory cell corresponding to the edge portion of the control gate electrode.   
     
     
         15 . The device of  claim 11 , wherein the charge storage layer is a charge trap layer. 
     
     
         16 . The device of  claim 11 , wherein the control gate electrode has another edge portion spaced farther apart from the blocking insulating layer than the central portion of the control gate electrode, and
 the edge portions of the control gate electrode are on opposing sides of the control gate electrode and face the blocking insulating layer.   
     
     
         17 . The device of  claim 16 , wherein the central portion of the control gate electrode is positioned between the edge portions of the control gate electrode. 
     
     
         18 . A memory device, comprising:
 a tunneling insulating layer on an active region;   a charge storage layer on the tunneling insulating layer;   a blocking insulating layer on the charge storage layer; and   a control gate electrode on the blocking insulating layer,   wherein the control gate electrode has an edge portion spaced farther apart from the blocking insulating layer than a central portion of the control gate electrode, and   wherein a surface of the control gate electrode, which faces the blocking insulating layer, has a convex surface curved towards the blocking insulating layer.   
     
     
         19 . The device of  claim 18 , wherein the edge portion of the control gate electrode has a thickness equal to, or smaller than, that of the central portion thereof, and
 the edge portion of the control gate electrode tapers outward towards a sidewall of the memory device and away from the blocking insulating layer.   
     
     
         20 . The device of  claim 18 , further comprising:
 at least two of the control gate electrodes; and   a bottom spacer between the at least two control gate electrodes, wherein the bottom spacer fills a region between the edge portion of the at least two control gate electrodes and the blocking insulating layer.   
     
     
         21 . The device of  claim 18 , further comprising:
 a gate dielectric material in the central portion of the memory cell corresponding to the central portion of the control gate electrode, wherein the gate dielectric material is thinner than that in an edge portion of the memory cell corresponding to the edge portion of the control gate electrode.   
     
     
         22 . The device of  claim 18 , wherein the charge storage layer is a charge trap layer. 
     
     
         23 . A memory device, comprising:
 a tunneling insulating layer on an active region;   a charge storage layer on the tunneling insulating layer;   a blocking insulating layer on the charge storage layer; and   a control gate electrode on the blocking insulating layer,   wherein the control gate electrode has an edge portion spaced farther apart from the blocking insulating layer than a central portion of the control gate electrode, and   wherein the central portion of the control gate electrode has a plane surface opposite the blocking insulating layer, and the edge portion of the control gate electrode has a concave surface that tapers outwards towards a sidewall of the memory device and away from the blocking insulating layer.   
     
     
         24 . The device of  claim 23 , wherein the edge portion of the control gate electrode has a thickness equal to, or smaller than, that of the central portion thereof, and
 the edge portion of the control gate electrode tapers outward towards a sidewall of the memory device and away from the blocking insulating layer.   
     
     
         25 . The device of  claim 23 , further comprising:
 at least two of the control gate electrodes; and   a bottom spacer between the at least two control gate electrodes, wherein the bottom spacer fills a region between the edge portion of the at least two control gate electrodes and the blocking insulating layer.   
     
     
         26 . The device of  claim 23 , further comprising:
 a gate dielectric material in the central portion of the memory cell corresponding to the central portion of the control gate electrode, wherein the gate dielectric material is thinner than that in an edge portion of the memory cell corresponding to the edge portion of the control gate electrode.   
     
     
         27 . The device of  claim 23 , wherein the charge storage layer is a charge trap layer. 
     
     
         28 . The device of  claim 23 , wherein the control gate electrode has another edge portion spaced farther apart from the blocking insulating layer than the central portion of the control gate electrode, and
 the edge portions of the control gate electrode are on opposing sides of the control gate electrode and face the blocking insulating layer.   
     
     
         29 . The device of  claim 28 , wherein the central portion of the control gate electrode is positioned between the edge portions of the control gate electrode.