US2016126264A1PendingUtilityA1

Semiconductor device and a method of manufacturing the same

Assignee: RENESAS ELECTRONICS CORPPriority: Nov 9, 2007Filed: Jan 12, 2016Published: May 5, 2016
Est. expiryNov 9, 2027(~1.3 yrs left)· nominal 20-yr term from priority
Inventors:Shinya Suzuki
H10W 99/00H10W 72/0198H10W 72/29H10W 72/932H10W 72/952H10W 72/923H10W 72/019H10W 72/01938H10W 72/981H10W 72/074H10W 72/07332H10W 72/073H10W 72/072H10W 72/241H10W 72/354H10W 72/352H10W 72/325H10W 90/724H10W 72/013H10W 72/248H10W 72/252H10W 72/242H10W 72/244H10W 72/232H10W 72/221H10W 72/01255H10W 72/01235H10W 90/734H10P 95/064H10P 50/283H10P 14/69433H10P 14/69215H10W 72/07237H10W 72/90H10W 20/092H10W 20/43H10W 20/40H10W 20/01G02F 1/1345H10D 30/601H10D 86/80H01L 24/05H01L 2224/05164H01L 2224/05144H01L 2224/05166H01L 2924/05042H01L 2924/05442H01L 2924/04941H01L 2924/0132H01L 2224/05075H01L 2224/05155H01L 2224/05184H01L 2224/05073H01L 2224/0401H01L 23/528H01L 27/13G02F 1/133302G02F 1/134309G02F 1/13306G02F 1/1368G02F 1/136286G02F 1/13458G02F 1/13439G02F 1/133345
60
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Claims

Abstract

A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.

Claims

exact text as granted — not AI-modified
1 - 18 . (canceled) 
     
     
         19 . A semiconductor device comprising:
 a first wiring formed over a semiconductor substrate;   a first insulating film formed over the first wiring;   a pad formed over the first insulating film and having a larger thickness than a thickness of the first wiring;   a second insulating film formed over the pad and the first insulating film;   a third insulating film formed over the second insulating film and formed of a different material from a material of the second insulating film;   an opening formed in the second and third insulating films such that the opening reaches the pad; and   a bump electrode electrically connected to the pad and formed over the pad and the third insulating film,   wherein a top surface of the second insulating film is located over a top surface of the pad and is flattened by a CMP method.   
     
     
         20 . A semiconductor device according the  claim 19 , wherein the second insulating film includes a silicon oxide film. 
     
     
         21 . A semiconductor device according the  claim 20 , wherein the third insulating film includes a silicon nitride film. 
     
     
         22 . A semiconductor device according the  claim 19 , wherein the bump electrode includes an under bump metal film and a metal film having larger thickness than the under bump metal film, and
 wherein the under bump metal film is formed between the metal film and the pad inside the opening, and is formed between the metal film and the third insulating film outside the opening.   
     
     
         23 . A semiconductor device according the  claim 22 ,
 wherein the under bump metal film is a single layer film or laminated film, the under bump metal film including one or more of titanium film, nickel film, palladium film, titanium-tungsten alloy film, titanium nitride film and/or gold film.   
     
     
         24 . A semiconductor device comprising:
 a plurality of wiring layers formed over a semiconductor substrate;   a pad formed in a top wiring layer of the wiring layers;   a surface protection film formed over the pad;   an opening formed in the surface protection film such that the opening reaches the pad; and   a bump electrode electrically connected to the pad such that a top surface of the bump electrode is located over a top surface of the surface protection film,   wherein the surface protection film includes a first film and a second film formed over the first film,   wherein the first film includes silicon and oxygen,   wherein the second film includes silicon and nitrogen and is formed of a different material from the first film, and   wherein a top surface of the first film is located over a top surface of the pad and is flattened by a polishing treatment.   
     
     
         25 . A semiconductor device according the  claim 24 , wherein the first film is formed of a silicon oxide film. 
     
     
         26 . A semiconductor device according the  claim 25 , wherein the second film is formed of a silicon nitride film. 
     
     
         27 . A semiconductor device according the  claim 24 , wherein the bump electrode includes an under bump metal film and a metal film having larger thickness than the under bump metal film. 
     
     
         28 . A semiconductor device according the  claim 27 , wherein the wherein the under bump metal film is a single layer film or laminated film, the under bump metal film including one or more of titanium film, nickel film, palladium film, titanium-tungsten alloy film, titanium nitride film and/or gold film.

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