Method of production of field-effect transistor with local source/drain insulation

Abstract

A method for fabricating a field-effect transistor with local source/drain insulation. The method includes forming and patterning a gate stack with a gate layer and a gate dielectric on a semiconductor substrate; forming source and drain depressions at the gate stack in the semiconductor substrate; forming a depression insulation layer at least in a bottom region and along the sidewalls of the source and drain depressions; and filling the at least partially insulated source and drain depressions with a filling layer for realizing source and drain regions.

1 . A method for fabricating a field-effect transistor with local source/drain insulation, comprising:
 forming and patterning a gate stack with a gate layer and a gate dielectric on a semiconductor substrate, wherein the gate dielectric is formed directly on the substrate surface and wherein the gate layer is formed at a surface of the gate dielectric;   forming source and drain depressions in the semiconductor substrate, wherein the gate stack is between the source and drain depressions;   forming a depression insulation layer having a depression bottom insulation layer at least across an entire bottom region of the source and drain depressions; and   filling the at least partially insulated source and drain depressions with an electrically conductive filling layer for realizing source and drain regions;   wherein the depression insulation layer further has a depression sidewall insulation layer, which is formed in a sidewall region of the source and drain depressions but does not touch the gate dielectric, and wherein the depression sidewall insulation layer overlaps both a portion of the gate dielectric and a portion of the gate layer, and further overlaps with a spacer at a sidewall of the gate layer such that the conductive filling layer is free from overlap with said spacer, and extends to an isolation trench formed in the semiconductor substrate, the isolation trench having a bottom surface that is at the same depth as a bottom surface of the depression sidewall insulation layer or below a bottom surface of the depression sidewall insulation layer.   
     
     
         2 . The method as claimed in  claim 1 , wherein a channel region is located between the source and drain regions, the channel region being a fully depleted channel region. 
     
     
         3 . The method as claimed in  claim 1 , wherein the depression sidewall insulation layer has a thickness in the range of 20 to 30 nm. 
     
     
         4 . The method as claimed in  claim 1 , wherein the depression sidewall insulation layer is formed by an oxidation of uncovered sidewalls of the source and drain depressions. 
     
     
         5 . The method as claimed in  claim 1 , wherein the depression sidewall insulation layer produces a pinch-off of a channel region resulting in a fully depleted structure in the channel region. 
     
     
         6 . The method as claimed in  claim 1 , wherein the electrically conductive filling layer has a seed layer for improving a deposition in the source and drain depressions. 
     
     
         7 . The method as claimed in  claim 1 , wherein a gate insulation layer is formed at sidewalls of the gate layer. 
     
     
         8 . The method as claimed in  claim 1 , wherein the field-effect transistor is bounded by shallow trench isolations. 
     
     
         9 . A method for fabricating a field-effect transistor with local source/drain insulation, having the following steps:
 a) forming and patterning a gate stack with a gate layer and a gate dielectric on a semiconductor substrate;   b) forming source and drain depressions at the gate stack in the semiconductor substrate;   c) forming a depression insulation layer at least in a bottom region of the source and drain depressions; and   d) filling the at least partially insulated source and drain depressions with a filling layer for realizing source and drain regions;   wherein the depression insulation layer has a depression sidewall insulation layer, which is formed in a sidewall region of the source and drain depressions but does not touch the gate dielectric.   
     
     
         10 . The method as claimed in  claim 9 , wherein a channel region is located between the source and drain regions, the channel region being a fully depleted channel region. 
     
     
         11 . The method as claimed in  claim 9 , wherein the depression sidewall insulation layer extends into a channel region below the gate dielectric. 
     
     
         12 . The method as claimed in  claim 9 , wherein the depression sidewall insulation layer has a thickness in the range of 20 to 30 nm. 
     
     
         13 . The method as claimed in  claim 9 , wherein the depression sidewall insulation layer is formed by an oxidation of uncovered sidewalls of the source and drain depressions. 
     
     
         14 . The method as claimed in  claim 9 , wherein the depression sidewall insulation layer produces a pinch-off of a channel region resulting in a fully depleted structure in the channel region. 
     
     
         15 . The method as claimed in  claim 9 , wherein the electrically conductive filling layer has a seed layer for improving a deposition in the source and drain depressions. 
     
     
         16 . The method as claimed in  claim 9 , wherein a gate insulation layer is formed at sidewalls of the gate layer. 
     
     
         17 . The method as claimed in  claim 9 , wherein the field-effect transistor is bounded by shallow trench isolations.