Semiconductor device

Abstract

To improve reliability of a semiconductor device obtained through a dicing step. In a ring region, a first outer ring is provided outside a seal ring, and a second outer ring is provided outside the first outer ring. This can prevent a crack from reaching even the seal ring that exists in the ring region, for example, when a scribe region located outside the ring region is cut off by a dicing blade.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 (a) a semiconductor substrate of quadrilateral shape having a pair of first opposed edges and a pair of second opposed edges;   (b) a seal ring formed over the semiconductor substrate so as to surround an integrated circuit forming region in plan view, the seal ring being formed of a multi-layered metal wirings;   (c) first dummy patterns formed over the semiconductor substrate which is positioned outside the seal ring in plan view, the first dummy patterns including a wiring layer formed of the same layer as a first one layer of the multi-layered metal wirings; and   (d) second dummy patterns formed over the semiconductor substrate which is positioned outside the seal ring in plan view, the second dummy patterns including a wiring layer formed of the same layer as a second one layer of the multi-layered metal wirings,   wherein the first dummy patterns are arranged along one of the pair of first opposed edges and one of the pair of second opposed edges,   wherein the second dummy patterns are arranged at a corner portion defined by the one of the pair of first opposed edges and the one of the pair of second opposed edges in plan view,   wherein the first dummy patterns have square shape in plan view,   wherein the second dummy patterns have rectangular shape and extend in a direction intersecting the one of the pair of first opposed edges and the one of the pair of second opposed edges in plan view, and   wherein a long edge of each of the second dummy patterns is longer than one edge of each of the first dummy patterns.   
     
     
         2 . A semiconductor device according to  claim 1 ,
 wherein a short edge of each of the second dummy patterns is shorter than one edge of each of the first dummy patterns.   
     
     
         3 . A semiconductor device according to  claim 1 ,
 wherein the first dummy patterns are arranged along the pair of first opposed edges and the pair of second opposed edges, and   wherein the second dummy patterns are arranged at four corner portions defined by the pair of first opposed edges and the pair of second opposed edges in plan view.   
     
     
         4 . A semiconductor device according to  claim 1 ,
 wherein the first and second dummy patterns are not connected to the semiconductor substrate.   
     
     
         5 . A semiconductor device according to  claim 1 ,
 wherein an upper most wiring layer is formed of the same layer as a pad, and   wherein the first and second dummy patterns are formed of at least one of lower wiring layers than the upper most wiring layer.   
     
     
         6 . A semiconductor device according to  claim 1 ,
 wherein the first dummy patterns includes wiring layers formed of the same layers as first adjacent layers of the multi-layered metal wirings respectively, the first adjacent layers being not connected to each other through plugs, and   wherein the second dummy patterns includes wiring layers formed of the same layers as second adjacent layers of the multi-layered metal wirings respectively, the second adjacent layers being connected to each other through plugs.