Processing method including pre-issue load-hit-store (lhs) hazard prediction to reduce rejection of load instructions
Abstract
A processing method supporting out-of-order execution (OOE) includes load-hit-store (LHS) hazard prediction at the instruction execution phase, reducing load instruction rejections and queue flushes at the dispatch phase. The instruction dispatch unit (IDU) detects likely LHS hazards by generating entries for pending stores in a LHS detection table. The entries in the table contain an address field (generally the immediate field) of the store instruction and the register number of the store. The ISU compares the address field and register number for each load with entries in the table to determine if a likely LHS hazard exists and if an LHS hazard is detected, the load is dispatched to the issue queue of the load-store unit (LSU) with a tag corresponding to the matching store instruction, causing the LSU to dispatch the load only after the corresponding store has been dispatched for execution.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A method of operation of a processor core, the method comprising:
fetching instructions of an instruction stream; dispatching instructions of the instruction stream by an instruction dispatch unit of the processor core that dispatches the instructions to issue queues, according to a type of the instructions; detecting likely load-hit-store hazards prior to the dispatch of load instructions to an issue queue of a load-store unit of the processor core; and identifying the likely load-hit-store hazards to the load-store unit, whereby rejections of the load instructions by the load-store unit due to load-hit-store hazards is reduced.
2 . The method of claim 1 , wherein the instruction dispatch unit detects store instructions of the instruction stream during the dispatching of the store instructions and stores store address information associated with the store instructions in corresponding entries in a load-hit-store detection table, and wherein the detecting likely load-hit-store hazards comprises detecting load instructions of the instruction stream and comparing the store address information of the entries in the table with load address information of load instructions of the instruction stream.
3 . The method of claim 2 , further comprising:
responsive to the detecting of a store operation, writing the store address information associated with the store operation to the load-hit-store detection table and dispatching the store operation to the issue queue of the load-store unit of the processor core; responsive to the detecting of a load instruction, comparing the load address information of the load instruction to entries in the load-hit-store detection table corresponding to store operations occurring earlier in the instruction stream to determine if a likely load-hit-store hazard exists between the load instruction and a given one of the store operations; responsive to the comparing determining that the likely load-hit-store hazard exists between the load instruction and the given store operation, dispatching the load instruction to the issue queue of the load-store unit of the processor core along with a tag identifying the given store operation; and responsive to the comparing determining that the likely load-hit-store hazard does not exist between the load instruction and the given store operation, dispatching the load instruction to the issue queue of the load-store unit of the processor core without the tag.
4 . The method of claim 2 , wherein the store address information is one or both of an immediate field of the store instruction and one or more base register numbers of the store instruction.
5 . The method of claim 3 , further comprising:
the load-store unit examining a next entry of the issue queue to determine whether or not a next operation is a load instruction with a corresponding tag; the load-store unit, responsive to determining that the load instruction with a corresponding tag is not present, processing the next entry for execution by the load-store unit; the load-store unit examining the next entry of the issue queue to determine whether or not the next operation is a store operation; the load-store unit, responsive to determining that the next operation is a store operation, examining the issue queue to determine whether a load instruction having a corresponding tag matching a tag of the store operation is present; the load-store unit, responsive to determining that the next operation is a store operation, processing the next entry for execution by the load-store unit; and the load-store unit, responsive to determining that the load instruction having the corresponding tag matching the tag of the store operation is present, processing the load instruction for execution by the load-store unit subsequent to processing the next entry.
6 . The method of claim 3 , further comprising:
responsive to detecting a store operation in the instruction stream, comparing entries in the load-hit-store detection table with the store address information of the store operation; and responsive to the comparing detecting a match between the store address information of the store instruction and an entry in the load-hit-store detection table, invalidating the entry in the load-hit-store detection table prior to the instruction dispatch unit storing an entry corresponding to the store instruction in the load-hit-store detection table, whereby only a single valid entry in the load-hit-store detection table contains identical store address information at any time.
7 . The method of claim 3 , wherein the comparing compares a most-recently-stored matching entry in the load-hit-store detection table that has a match between the load address information of the load instruction and the most-recently-stored matching entry in the load-hit-store detection table, whereby multiple valid entries in the load-hit-store detection table may match a particular load address information, without causing a load-hit-store hazard.Join the waitlist — get patent alerts
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