Ad converter

Abstract

A successive approximation type AD converter includes: a comparator comparing an analog input signal and a DA-converted comparison code; and a control circuit. When an output of the comparator settles before a limit time period has passed since the comparator started a comparison operation, the control circuit updates the comparison code on the basis of the settled output of the comparator. When the limit time period has passed before the output of the comparator settles, the control circuit updates the comparison code not on the basis of the present output of the comparator.

1 . A successive approximation type AD (Analog-to-Digital) converter comprising:
 a DA (Digital-to-Analog) converter that convert a comparison code;   a comparator that compares an analog input signal and an output signal of said DA converter responding to a clock signal; and   a control circuit, wherein   said control circuit includes:
 a first determination unit for outputting a first determination signal corresponding to an output of the comparator; 
 a second determination unit for outputting a second determination signal responding the clock signal; and 
 a first control unit for updating said comparison code responding to said first and second determination signals. 
   
     
     
         2 . The AD converter according to  claim 1 , wherein
 said first determination unit outputs said first determination signal asserted when the output of said comparator settles;   said second determination unit generates said second determination signal asserted when said limit time period has passed since said comparator started the comparison operation; and   said first control unit updates said comparison code when at least one of said first and second determination signals is asserted.   
     
     
         3 . The AD converter according to  claim 2 , wherein
 said comparator starts the comparison operation when said clock signal is asserted,   said control circuit further includes a second control unit for generating said clock signal, and   said second control unit is configured to negate said clock signal in response to assertion of at least one of said first and second determination signals, and to assert said clock signal when a predetermined time period has passed since said clock signal was negated.   
     
     
         4 . The AD converter according to  claim 3 , wherein said second determination unit negates said second determination signal when said clock signal is negated. 
     
     
         5 . The AD converter according to  claim 4 , wherein
 said second determination unit includes:   a delay circuit for delaying timing of each of rise and fall of said clock signal by said limit time period; and   a first logic gate for generating said second determination signal asserted when said clock signal is asserted and an output signal of said delay circuit is asserted.   
     
     
         6 . The AD converter according to  claim 4 , wherein
 said second determination unit includes:   a delay circuit for delaying timing of each of rise and fall of said clock signal by said limit time period; and   a D latch circuit having: an input terminal for receiving said clock signal; an inversion reset terminal for receiving said clock signal; a clock terminal for receiving an output signal of said delay circuit; and an output terminal for outputting said second determination signal.   
     
     
         7 . The AD converter according to  claim 5 , wherein a delay time of said delay circuit is adjustable in accordance with a set value of a register. 
     
     
         8 . The AD converter according to  claim 3 , wherein said comparator is configured to:
 output a comparison result by a differential signal formed of a positive phase signal and a negative phase signal;   fix each of said positive phase signal and said negative phase signal to a first logic level when said clock signal is negated; and   decide the output by changing one of said positive phase signal and said negative phase signal into a second logic level when said clock signal is asserted,   said first determination unit includes a second logic gate for generating said first determination signal, and   said second logic gate asserts said first determination signal when one of said positive phase signal and said negative phase signal is at said first logic level and the other of said positive phase signal and said negative phase signal is at said second logic level.   
     
     
         9 . The AD converter according to  claim 8 , wherein
 said second determination unit includes:
 a replica comparator that is identical in configuration to said comparator, and outputs, when a predetermined input voltage is input and said clock signal is asserted, a differential output signal according to the input voltage; and 
 a replica logic gate that is identical in configuration to said second logic gate, and generates said second determination signal based on the differential output signal of said replica comparator, and 
   said limit time period is determined in accordance with an input voltage of said replica comparator.   
     
     
         10 . The AD converter according to  claim 9 , wherein the input voltage of said replica comparator is equal to one half of a voltage corresponding to a least significant bit of said AD converter. 
     
     
         11 . The AD converter according to  claim 8 , wherein said second logic gate includes an exclusive-OR gate. 
     
     
         12 . The AD converter according to  claim 8 , wherein
 said AD converter further includes an SR latch circuit into which said positive phase signal and said negative phase signal from said comparator are input,   an internal state of said SR latch circuit does not change when each of said positive phase signal and said negative phase signal is at said first logic level, and changes into a set state or a reset state in response to a change of one of said positive phase signal and said negative phase signal into said second logic level, and   said first control unit generates said comparison code, based on an output signal of said SR latch circuit.   
     
     
         13 . The AD converter according to  claim 6 , wherein a delay time of said delay circuit is adjustable in accordance with a set value of a register.