Method for reading a third-dimensional embedded re-writeable non-volatile memory and registers

Abstract

A non-volatile register includes register logic connected with first and second ends of a memory element. The register logic is positioned below the memory element. The memory element may be a two-terminal memory element configured to store data as a plurality of conductivity profiles that can be non-destructively determined by applying a read voltage across the two terminals. New data can be written to the two-terminal memory element by applying a write voltage of a predetermined magnitude and/or polarity across the two terminals. The two-terminal memory element retains stored data in the absence of power. A reference element including a structure that is identical or substantially identical to the two-terminal memory element may be used to generate a reference signal for comparisons during read operations.

1 . A method, comprising:
 receiving a datum; and   applying a voltage across a memory element to write the datum to the memory element;   wherein the memory element is configured to store the datum as one of a plurality of conductivity profiles and to retain the datum in an absence of electrical power;   wherein the applying the voltage is operative to change a resistive state of the memory element from one of the plurality of conductivity profiles to another one of the plurality of conductivity profiles; and   wherein the voltage has a polarity operative to change the resistive state of the memory element.   
     
     
         2 . The method of  claim 1 , further comprising:
 switching the polarity of the voltage based on the datum.   
     
     
         3 . The method of  claim 1 ,
 wherein the memory element includes:
 a conductive oxide including mobile oxygen ions; and 
 an electrolytic tunnel barrier in contact with the conductive oxide; 
   wherein the conductive oxide and the electrolytic tunnel barrier are electrically serially coupled with memory element.   
     
     
         4 . The method of  claim 1 ,
 wherein the memory element is integrally fabricated directly above a silicon substrate;   wherein the silicon substrate includes circuitry fabricated on the silicon substrate; and   wherein the circuitry includes register logic electrically coupled with the memory element.   
     
     
         5 . The method of  claim 4 , wherein the memory element is embedded in a memory plane that is integrally fabricated directly above and is in direct contact with the silicon substrate. 
     
     
         6 . The method of  claim 5 ,
 wherein the memory plane includes a two-terminal cross-point array having a plurality of conductive array lines, the memory element being positioned between a cross-point of a unique pair of the conductive array lines;   wherein first and second terminals of the memory element are electrically coupled with the unique pair of the conductive array lines;   wherein the memory element is directly electrically in series with the unique pair of conductive array lines; and   wherein the unique pair of conductive array lines electrically couples the memory element with the register logic.   
     
     
         7 . A system, comprising:
 a receiver circuit to receive a datum; and   a voltage circuit configured to write the datum to a memory element configured to store the datum as one of a plurality of conductivity profiles and to retain the datum in the absence of electrical power;   wherein the memory element comprises:
 a conductive oxide including mobile oxygen ions; and 
 an electrolytic tunnel barrier electrically in series with the conductive oxide. 
   
     
     
         8 . The system of  claim 7 ,
 wherein the electrolytic tunnel barrier comprises a thickness that is less than approximately 50 angstroms.   
     
     
         9 . The system of  claim 7 ,
 wherein:
 the memory element is integrally fabricated directly above a silicon substrate; 
 the silicon substrate comprises circuitry fabricated on the silicon substrate; and 
 the circuitry comprises a register logic electrically coupled with the memory element. 
   
     
     
         10 . The system of  claim 7 ,
 wherein the voltage circuit is further configured to write the datum to the memory element by applying a voltage.   
     
     
         11 . The system of  claim 10 ,
 wherein the voltage circuit is further configured to switch a polarity of the voltage based on the datum.   
     
     
         12 . A method, comprising:
 receiving a datum; and   applying a voltage across a memory element to write the datum to the memory element;   wherein the memory element is configured to store the datum as one of a plurality of conductivity profiles and to retain the datum in an absence of electrical power; and   wherein the memory element comprises:
 a conductive oxide including mobile oxygen ions; and 
 an electrolytic tunnel barrier electrically in series with the conductive oxide. 
   
     
     
         13 . The method of  claim 12 , further comprising:
 switching a polarity of the voltage based on the datum.   
     
     
         14 . The method of  claim 12 , further comprising:
 serially coupling the conductive oxide and the electrolytic tunnel barrier to the memory element.   
     
     
         15 . The method of  claim 12 , further comprising:
 fabricating the memory element directly above a silicon substrate; and   fabricating circuitry register logic electrically coupled with the memory element on the silicon substrate.   
     
     
         16 . The method of  claim 15 , further comprising:
 embedding the memory element in a memory plane that is integrally fabricated directly above and is in direct contact with the silicon substrate.   
     
     
         17 . The method of  claim 16 ,
 wherein the memory plane includes a two-terminal cross-point array having a plurality of conductive array lines, the memory element being positioned between a cross-point of a unique pair of the conductive array lines;   wherein first and second terminals of the memory element are electrically coupled with the unique pair of the conductive array lines;   wherein the memory element is directly electrically in series with the unique pair of conductive array lines; and   wherein the unique pair of conductive array lines electrically couples the memory element with the register logic.