Semiconductor storage device

Abstract

A semiconductor storage device including a first power supply line; a second power supply line; a first bit line; a second bit line; a first load transistor having a source coupled to the first power supply line, a drain and a gate; a second load transistor having a source coupled to the first power supply line, a drain and a gate; a first drive transistor having a source coupled to the second power supply line, a drain and a gate; a second drive transistor having a source coupled to the second power supply line, a drain and a gate; a first transfer transistor having one terminal coupled to the drain of the first drive transistor and another terminal coupled to the first bit line.

What is claimed is: 
     
         1 . A semiconductor storage device comprising:
 a first power supply line;   a second power supply line;   a first bit line;   a second bit line;   a first load transistor having a source coupled to the first power supply line, a drain and a gate;   a second load transistor having a source coupled to the first power supply line, a drain and a gate;   a first drive transistor having a source coupled to the second power supply line, a drain and a gate;   a second drive transistor having a source coupled to the second power supply line, a drain and a gate;   a first transfer transistor having one terminal coupled to the drain of the first drive transistor and another terminal coupled to the first bit line;   a second transfer transistor having one terminal connected to the drain of the second drive transistor and another terminal coupled to the second bit line;   a first cell node line which is coupled to the drain of the first load transistor, the drain of the first drive transistor, the gate of the second load transistor, the gate of the second drive transistor and the one terminal of the first transfer transistor; and   a second cell node line which is coupled to the drain of the second load transistor, the drain of the second drive transistor, the gate of the first load transistor, the gate of the first drive transistor and the one terminal of the second transfer transistor,   wherein   the first cell node line and the first bit line are formed in different wiring layers, and have a first wide portion at a portion where the first cell node line and the first bit line overlap each other in a plane view,   the second cell node line and the second bit line are formed in different wiring layers, and have a second wide portion at a portion where the second cell node line and the second bit line overlap each other in the plane view,   the first wide portion is formed with a line width greater than that of other portions of the first bit line, and   the second wide portion is formed with a line width greater than that of other portions of the second bit line.   
     
     
         2 . The semiconductor storage device according to  claim 1 , wherein
 the first bit line is formed with a longitudinal direction thereof set in a direction perpendicular to a longitudinal direction of the first cell node line, and   the second bit line is formed with a longitudinal direction thereof set in a direction perpendicular to a longitudinal direction of the second cell node line.   
     
     
         3 . The semiconductor storage device according to  claim 1 , further comprising:
 a first wiring layer in which the first cell node line and the second cell node line are formed;   a second wiring layer in which the first bit line and the second bit line are formed; and   an interlayer insulating film formed between the first wiring layer and the second wiring layer, wherein   in the first wide portion, a first capacitor is formed between the first cell node line and the first bit line, the first capacitor functioning using the interlayer insulating film as a dielectric film, and   in the second wide portion, a second capacitor is formed between the second cell node line and the second bit line, the second capacitor functioning using the interlayer insulating film as a dielectric film.   
     
     
         4 . The semiconductor storage device according to  claim 1 ,
 wherein a distance between the first power supply line and a first side opposed to the first power supply line in the first wide portion is shorter than a distance between the first power supply line and a second side opposed to the first power supply line in a portion other than the first wide portion of the first bit line.   
     
     
         5 . The semiconductor storage device according to  claim 1 ,
 wherein assuming that the longitudinal direction of the first bit line is a first direction, a width in the first direction of the first wide portion is formed to be greater than that in the first direction of the first cell node line.   
     
     
         6 . A semiconductor storage device comprising:
 a first power supply line;   a second power supply line;   a first bit line;   a second bit line;   a first load transistor having a source coupled to the first power supply line, a drain and a gate;   a second load transistor having a source coupled to the first power supply line, a drain and a gate;   a first drive transistor having a source coupled to the second power supply line, a drain and a gate;   a second drive transistor having a source connected to the second power supply line, a drain and a gate;   a first transfer transistor having one terminal coupled to the drain of the first drive transistor, and another terminal coupled to the first bit line;   a second transfer transistor having one terminal coupled to the drain of the second drive transistor, and another terminal coupled to the second bit line;   a first cell node line which is coupled to the drain of the first load transistor, the drain of the first drive transistor, the gate of the second load transistor, the gate of the second drive transistor and the one terminal of the first transfer transistor;   a second cell node line which is coupled to the drain of the second load transistor, the drain of the second drive transistor, the gate of the first load transistor, the gate of the first drive transistor and the one terminal of the second transfer transistor;   a first capacitor line coupled to the first cell node line through a via hole, the first capacitor line being located at a position adjacent to the first bit line in the same wiring layer as that of the first bit line and formed with a longitudinal direction of the first capacitor line set in a direction parallel to the first bit line; and   a second capacitor line connected to the second cell node line through a via hole, the second capacitor line being located at a position adjacent to the second bit line in the same wiring layer as that of the second bit line and formed with a longitudinal direction of the second capacitor line set in a direction parallel to the second bit line,   wherein   the first cell node line and the first bit line are formed in different wiring layers and have a portion where the first cell node line and the first bit line overlap each other when viewed from above, and   the second cell node line and the second bit line are formed in different wiring layers and have a portion where the second cell node line and the second bit line overlap each other when viewed from above.   
     
     
         7 . The semiconductor storage device according to  claim 6 , wherein
 the first bit line is formed with a longitudinal direction thereof set in a direction perpendicular to a longitudinal direction of the first cell node line, and   the second bit line is formed with a longitudinal direction thereof set in a direction perpendicular to a longitudinal direction of the second cell node line.   
     
     
         8 . The semiconductor storage device according to  claim 6 , further comprising:
 a first wiring layer in which the first cell node line and the second cell node line are formed;   a second wiring layer in which the first bit line, the second bit line, the first capacitor line, and the second capacitor line are formed;   a first interlayer insulating film formed between the first wiring layer and the second wiring layer;   a second interlayer insulating film formed between the second wiring layer and a third wiring layer formed above the second wiring layer, wherein   in the portion where the first cell node line and the first bit line overlap each other, a first divided capacitor is formed, the first divided capacitor functioning using the first interlayer insulating film as a dielectric film and constituting a first capacitor provided between the first cell node line and the first bit line, and   between the first bit line and the first capacitor line, a second divided capacitor is formed, the second divided capacitor functioning using the second interlayer insulating film as a dielectric film and constituting the first capacitor provided between the first cell node line and the first bit line,   in the portion where the second cell node line and the second bit line overlap each other, a third divided capacitor is formed, the third divided capacitor functioning using the first interlayer insulating film as a dielectric film and constituting a second capacitor provided between the second cell node line and the second bit line,   between the second bit line and the second capacitor line, a fourth divided capacitor is formed, the fourth divided capacitor functioning using the second interlayer insulating film as a dielectric film and constituting the second capacitor provided between the second cell node line and the second bit line.   
     
     
         9 . The semiconductor storage device according to  claim 6 ,
 wherein the first capacitor line and the second capacitor line are formed in a region in which a memory cell of the semiconductor storage device is formed.   
     
     
         10 . The semiconductor storage device according to  claim 6 ,
 wherein the first capacitor line and the second capacitor line are each disposed at a position closer to the first power supply line than the first bit line and the second bit line.   
     
     
         11 . The semiconductor storage device according to  claim 6 ,
 wherein the first capacitor line and the second capacitor line are each disposed at a position farther from the first power supply line than the first bit line and the second bit line.   
     
     
         12 . A semiconductor storage device comprising:
 a first power supply line;   a second power supply line;   a first bit line;   a second bit line;   a first load transistor having a source coupled to the first power supply line, a drain and a gate;   a second load transistor having a source coupled to the first power supply line, a drain and a gate;   a first drive transistor having a source coupled to the second power supply line, a drain and a gate;   a second drive transistor having a source connected to the second power supply line, a drain and a gate;   a first transfer transistor having one terminal coupled to the drain of the first drive transistor, and another terminal coupled to the first bit line;   a second transfer transistor having one terminal coupled to the drain of the second drive transistor, and another terminal coupled to the second bit line;   a first cell node line which is coupled to the drain of the first load transistor, the drain of the first drive transistor, the gate of the second load transistor, the gate of the second drive transistor and the one terminal of the first transfer transistor;   a second cell node line which is coupled to the drain of the second load transistor, the drain of the second drive transistor, the gate of the first load transistor, the gate of the first drive transistor and the one terminal of the second transfer transistor;   wherein   the first cell node line and the first bit line are formed in different wiring layers and have a first wide portion at a portion where the first cell node line and the first bit line overlap each other when viewed from above,   the second cell node line and the second bit line are formed in different wiring layers and have a second wide portion at a portion where the second cell node line and the second bit line overlap each other when viewed from above,   the first wide portion is formed at the first cell node line below the first bit line so as to extend in a direction in which the first bit line extends, and   the second wide portion is formed at the second cell node line below the second bit line so as to extend in a direction in which the second bit line extends.