Semiconductor memory device

Abstract

Proposed as a configuration, a controlling method, and a testing method for a ferroelectric shadow memory are (1) a bit line non-precharge method, in which no precharging of a bit line is performed during a read/write operation; (2) a plate line charge share method, in which electric charge is shared between plate lines that are driven sequentially during store/recall operation; (3) a word line boost method, in which the potential on a word line is raised during a write operation; (4) a plate line driver boost method, in which the driving capacity of a plate line driver is raised during a store/recall operation; and (5) a testing method for detecting a defect in a ferroelectric capacitor by arbitrarily setting a potential on a bit line from outside a chip.

What is claimed is: 
     
         1 . A semiconductor memory device comprising:
 a plurality of memory cells;   a word line commonly connected to the plurality of memory cells;   a plurality of bit lines and a plurality of inverted bit lines respectively connected to the plurality of memory cells; and   a memory controller operable to control access to the plurality of memory cells,   wherein the plurality of memory cells each include:
 an inverter loop connected between a first node and a second node; 
 a first access transistor connected between the first node and a bit line, the first access transistor being turned on and off according to a voltage applied to the word line; 
 a second access transistor connected between the second node and an inverted bit line, the second access transistor being turned on and off according to a voltage applied to the word line; 
 a first node capacitor connected to the first node, the first node capacitor having a higher capacitance than a parasitic capacitor of the bit line; and 
 a second node capacitor connected to the second node, the second node capacitor having a higher capacitance than a parasitic capacitor of the inverted bit line, and 
   wherein, when accessing a memory cell that is a target of a read/write, the memory controller drives the word line to turn on the first and second access transistors without precharging a bit line and an inverted bit line that are connected to a memory cell that is not a target of the read/write.   
     
     
         2 . The semiconductor memory device according to  claim 1 , further comprising:
 a plurality of transmission gates connected respectively between the plurality of bit lines and the plurality of inverted bit lines,   wherein, when accessing the memory cell that is a target of the read/write, the memory controller turns on a transmission gate between a bit line and an inverted bit line that are connected to a memory cell that is not a target of the read/write.   
     
     
         3 . The semiconductor memory device according to  claim 1 ,
 wherein the first and second node capacitors are ferroelectric capacitors connected between a plate line and the first and second nodes respectively, and   wherein, when restoring/recalling data in a memory cell, the memory controller pulse-drives the plate line.   
     
     
         4 . A semiconductor memory device comprising:
 a plurality of memory cells;   a plurality of plate lines respectively connected to the plurality of memory cells;   a plate line driver operable to drive the plurality of plate lines individually; and   a memory controller operable to control access to the plurality of memory cells,   wherein the plurality of memory cells each include:
 an inverter loop connected between a first node and a second node; 
 a first access transistor connected between the first node and a bit line; 
 a second access transistor connected between the second node and an inverted bit line; 
 a first ferroelectric capacitor connected between the first node and a plate line; and 
 a second ferroelectric capacitor connected between the second node and the plate line, 
   wherein, when restoring/recalling data in the memory cells, the memory controller pulse-drives the plurality of plate lines sequentially by use of the plate line driver and meanwhile, before pulse-driving an uncharged plate line by use of the plate line driver, the memory controller performs charge sharing between a charged plate line and the uncharged plate line.   
     
     
         5 . The semiconductor memory device according to  claim 4 , further comprising:
 a plurality of transmission gates each connected between adjacent plate lines,   wherein, before pulse-driving the uncharged plate line by use of the plate line driver, the memory controller turns on a transmission gate between the charged plate line and the uncharged plate line.   
     
     
         6 . A word line driver comprising:
 an output stage operable to drive a word line of a memory cell according to a word line enable signal; and   a boost stage operable to raise a voltage applied to the word line to higher than a supply voltage to the output stage by driving a ferroelectric capacitor according to a boost enable signal.   
     
     
         7 . The word line driver according to  claim 6 ,
 wherein the output stage includes:
 an inverter of which an input terminal is connected to a node to which the word line enable signal is applied; 
 a first transistor of a P-channel type of which a source is connected to a supply voltage node and a gate is connected to an output terminal of the inverter; and 
 a second transistor of an N-channel type of which a drain is connected to the word line, a source is connected to a ground node, and a gate is connected to the output terminal of the inverter, and 
   wherein the boost stage includes:
 a third transistor of a P-channel type of which a source is connected to the drain of the first transistor, a drain is connected to the word line, and a gate is connected to a node to which the boost enable signal is applied; and 
 a ferroelectric capacitor connected between the node to which the boost enable signal is applied and the word line. 
   
     
     
         8 . A semiconductor memory device comprising:
 a memory cell;   a memory controller operable to control access to the memory cell; and   the word line driver according to  claim 6  operable to drive the word line of the memory cell.   
     
     
         9 . The semiconductor memory device according to  claim 8 , further comprising:
 a delay stage operable to generate the boost enable signal by delaying the word line enable signal by a predetermined delay time.   
     
     
         10 . The semiconductor memory device according to  claim 9 ,
 wherein the delay stage includes an inverter chain.   
     
     
         11 . The semiconductor memory device according to  claim 8 ,
 wherein the memory cell includes:
 an inverter loop connected between a first node and a second node; 
 a first access transistor connected between the first node and a bit line, the first access transistor being turned on and off according to a voltage applied to the word line; 
 a second access transistor connected between the second node and an inverted bit line, the second access transistor being turned on and off according to a voltage applied to the word line; 
 a first node capacitor connected to the first node, the first node capacitor having a higher capacitance than a parasitic capacitor of the bit line; and 
 a second node capacitor connected to the second node, the second node capacitor having a higher capacitance than a parasitic capacitor of the inverted bit line. 
   
     
     
         12 . The semiconductor memory device according to  claim 11 ,
 wherein the first and second node capacitors are ferroelectric capacitors connected between a plate line and the first and second nodes respectively, and   wherein, when restoring/recalling data in a memory cell, the memory controller pulse-drives the plate line.   
     
     
         13 . A plate line driver comprising:
 a first output stage operable to generate a second plate line enable signal according to a first plate line enable signal;   a second output stage operable to drive a plate line of a memory cell according to the second plate line enable signal; and   a boost stage operable to augment driving capacity of the second output stage by lowering the second plate line enable signal to a negative voltage by driving a ferroelectric capacitor according to a boost enable signal.   
     
     
         14 . The plate line driver according to  claim 13 ,
 wherein the first output stage includes:
 a first transistor of a P-channel type of which a source is connected to a supply voltage node, a gate is connected to a node to which the first plate line enable signal is applied, and a drain is connected to a node to which the second plate line enable signal is applied; and 
 a second transistor of an N-channel type of which a source is connected to a ground node and a gate is connected to the node to which the first plate line enable signal is applied, 
   wherein the second output stage includes:
 a third transistor of a P-channel type of which a source is connected to the supply voltage node, a drain is connected to the plate line, and a gate is connected to the node to which the second plate line enable signal is applied; and 
 a fourth transistor of an N-channel type of which a drain is connected to the plate line, a source is connected to the ground node, and a gate is connected to the node to which the second plate line enable signal is applied, and 
   wherein the boost stage includes:
 an inverter of which an input terminal is connected to a node to which the boost enable signal is applied; 
 a fifth transistor of an N-channel type of which a drain is connected to the node to which the second plate line enable signal is applied, a source is connected to the drain of the second transistor, and a gate is connected to an output terminal of the inverter; and 
 a ferroelectric capacitor connected between the output terminal of the inverter and the node to which the second plate line enable signal is applied. 
   
     
     
         15 . A semiconductor memory device comprising:
 a memory cell;   a memory controller operable to control access to the memory cell; and   the plate line driver according to  claim 13  operable to drive a plate line of the memory cell.   
     
     
         16 . The semiconductor memory device according to  claim 15 ,
 wherein the memory cell includes:
 an inverter loop connected between a first node and a second node; 
 a first access transistor connected between the first node and a bit line; 
 a second access transistor connected between the second node and an inverted bit line; 
 a first ferroelectric capacitor connected between the first node and a plate line; and 
 a second ferroelectric capacitor connected between the second node and the plate line, and 
   wherein, when restoring/recalling data in a memory cell, the memory controller pulse-drives the plate line.   
     
     
         17 . A semiconductor memory device comprising:
 an inverter loop connected between a first node and a second node;   a first access transistor connected between the first node and a bit line;   a second access transistor connected between the second node and an inverted bit line;   a first ferroelectric capacitor connected between the first node and a plate line;   a second ferroelectric capacitor connected between the second node and the plate line; and   an external terminal operable to apply arbitrary analog voltages to the bit line and the inverted bit line respectively.   
     
     
         18 . The semiconductor memory device, further comprising, independently of each other:
 a first word line connected to a gate of the first access transistor; and   a second word line connected to a gate of the second access transistor.   
     
     
         19 . A method for testing the semiconductor memory device according to  claim 17 , the method comprising:
 a step of applying an arbitrary reference voltage to one of the bit line and the inverted bit line via the external terminal;   a step of pulse-driving the plate line with the inverter loop disabled;   a step of turning on both of the first and second access transistors or only one of the first and second access transistors to which the reference voltage is not applied; and   a step of comparing voltages between the bit line and the inverted bit line.   
     
     
         20 . A method for testing the semiconductor memory device according to  claim 17 , the method comprising:
 a step of applying an arbitrary offset voltage to one of the bit line and the inverted bit line via the external terminal;   a step of turning on the first and second access transistors;   a step of pulse-driving the plate line with the inverter loop disabled;   a step of enabling the inverter loop; and   a step of comparing voltages between the bit line and the inverted bit line.