Semiconductor device having identification information generating function and identification information generation method for semiconductor device

Abstract

A semiconductor device includes an identification information generation circuit having a power supply control circuit whose output voltage is controlled by a control signal, and a memory array having a first cell power line and a second cell power line. The power supply control circuit outputs a first supply voltage and a second supply voltage to a first cell power line and a second power line, respectively, when the control signal is in a first state, and outputs an intermediate voltage to the first cell power line and the second cell power line when the control signal is in a second state.

What is claimed is: 
     
         1 . A semiconductor device comprising an identification information generation circuit including
 a power supply control circuit having a first input node to which a first control signal is applied, a first power supply voltage output node, a second power supply voltage output node, and a third power supply voltage output node, and   a memory array having a bit line pair, a word line, a memory cell connected to said bit line pair and said word line, and a first cell power line, a second cell power line and a third cell power line connected to said memory cell,   said first cell power line, said second cell power line and said third cell power line being connected to said first power supply voltage output node, said second power supply voltage output node and said third power supply voltage output node, respectively,   said memory cell having a first conductivity type MOS transistor and a second conductivity type MOS transistor,   said power supply control circuit being configured to output a first supply voltage to said first power supply voltage output node and said second power supply voltage output node and a second supply voltage to said third power supply voltage output node when said first control signal is in a first state, and   output an intermediate voltage to said first power supply voltage output node, said second power supply voltage output node and said third power supply voltage output node when said first control signal is in a second state, said intermediate voltage having a value higher than a value obtained by adding an absolute value of a threshold voltage of said first conductivity type MOS transistor to said first supply voltage and lower than a value obtained by subtracting an absolute value of a threshold voltage of said second conductivity type MOS transistor from said second supply voltage.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein, in response to a change of said first control signal from said second state to said first state, said power supply control circuit drops electric potentials at said first cell power line and said second cell power line from said intermediate voltage to said first supply voltage at electric potential dropping speeds different from each other. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein
 said memory array further has a bit line intermediate voltage supply circuit connected to said bit line pair, and   in response to a change of said first control signal from said first state to said second state, said bit line intermediate voltage supply circuit supplies said intermediate voltage to said bit line pair.   
     
     
         4 . The semiconductor device according to  claim 3 , wherein, in a period in which said bit line intermediate voltage supply circuit supplies said intermediate voltage to said bit line pair, said word line selects said memory cell by a pulse signal having an amplitude greater than a difference between said first supply voltage and said second supply voltage.