Semiconductor device

Abstract

In order to reduce parasitic inductance of a main circuit in a power supply circuit, a non-insulated DC-DC converter is provided having a circuit in which a power MOS·FET for a high-side switch and a power MOS·FET for a low-side switch are connected in series. In the non-insulated DC-DC converter, the power MOS·FET for the high-side switch is formed by a p channel vertical MOS·FET, and the power MOS·FET for the low-side switch is formed by an n channel vertical MOS·FET. Thus, a semiconductor chip formed with the power MOS·FET for the high-side switch and a semiconductor chip formed with the power MOS·FET for the low-side switch are mounted over the same die pad and electrically connected to each other through the die pad.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a first semiconductor chip which includes a P-channel MOSFET including a source, a gate and a drain;   a second semiconductor chip which includes a N-channel MOSFET including a source, a gate and a drain;   a third semiconductor chip which includes a driver circuit for driving a gate of the P-channel MOSFET and a gate of the N-channel MOSFET;   a resin encapsulator encapsulating the first, second and third semiconductor chips;   an input power supply terminal exposed from the resin encapsulator and configured to be used for receiving an input power;   a reference potential supply terminal exposed from the resin encapsulator and configured to be used for supplying a reference potential; and   an output terminal exposed from the resin encapsulator and configured to be used for outputting an output,   wherein the source and the drain of the P-channel MOSFET are coupled to the input power supply terminal and the output terminal, respectively,   wherein the drain and the source of the N-channel MOSFET are coupled to the output terminal and the reference potential supply terminal, respectively, and   wherein the drain of the P-channel MOSFET and the drain of the P-channel MOSFET are electrically and mechanically coupled to a metal material which is electrically coupled to the output terminal.   
     
     
         2 . A semiconductor device according to  claim 1 ,
 wherein the metal material is comprised of copper.   
     
     
         3 . A semiconductor device according to  claim 1 ,
 wherein the first semiconductor chip and the second semiconductor chip are coupled to the metal material via paste.   
     
     
         4 . A semiconductor device according to  claim 1 ,
 wherein the resin encapsulator has a top surface and a bottom surface opposite the top surface, and   wherein the input power supply terminal, the reference potential supply terminal and the output terminal are exposed from the bottom surface of the resin body.   
     
     
         5 . A semiconductor device according to  claim 4 ,
 wherein the first semiconductor chip includes a source electrode pad which is electrically coupled to the source of the P-channel MOSFET, and   wherein the source electrode pad faces toward the top surface of the resin encapsulator.   
     
     
         6 . A semiconductor device according to  claim 1 ,
 wherein the second semiconductor chip includes a drain electrode which is electrically coupled to the drain of the N-channel MOSFET, and   wherein the drain electrode is mechanically coupled to the metal material.   
     
     
         7 . A semiconductor device according to  claim 1 ,
 wherein the gate of the P-channel MOSFET is electrically coupled to the driver circuit via a first wire, and   wherein the gate of the N-channel MOSFET is electrically coupled to the driver circuit via a second wire.   
     
     
         8 . A semiconductor device according to  claim 7 ,
 wherein the first semiconductor chip has a rectangular shape in plan view, with a pair of long sides and a pair of short sides, and   wherein the first wire is disposed so as to overlap one of the short sides of the first semiconductor chip.   
     
     
         9 . A semiconductor device according to  claim 1 ,
 wherein the first semiconductor chip has a rectangular shape in plan view, with a pair of long sides and a pair of short sides, and   wherein said one long side of the first semiconductor chip is arranged such that a closest distance between the second semiconductor chip and said one long side is less than a closest distance between the second semiconductor chip and the other long side.   
     
     
         10 . A semiconductor device comprising:
 a first semiconductor chip which includes a P-channel MOSFET including a source, a gate and a drain;   a second semiconductor chip which includes a N-channel MOSFET including a source, a gate and a drain;   a third semiconductor chip which includes a driver circuit for driving a gate of the P-channel MOSFET and a gate of the N-channel MOSFET;   a resin encapsulator encapsulating the first, second and third semiconductor chips;   an input power supply terminal exposed from the resin encapsulator and configured to be used for supplying an input power;   a reference potential supply terminal exposed from the resin encapsulator and configured to be used for receiving a reference potential;   an output terminal exposed from the resin encapsulator and configured to be used for outputting an output;   wherein the source and the drain of the P-channel MOSFET are coupled to the input power supply terminal and the output terminal, respectively,   wherein the drain and the source of the N-channel MOSFET are coupled to the output terminal and the reference potential supply terminal, respectively,   wherein the drain of the P-channel MOSFET and the drain of the N-channel MOSFET are electrically and mechanically coupled to a metal material which is electrically coupled to the output terminal,
 wherein the P-channel MOSFET comprises:
 a semiconductor substrate of the first semiconductor chip having a first surface and a second surface; 
 a trench formed to extend from the first surface of the semiconductor substrate toward the second surface thereof; 
 a gate insulating film formed over an inner wall surface of the trench; 
 a gate electrode, as the gate, formed over the gate insulating film; 
 p type semiconductor regions, as the source, which are formed in the first surface and formed at both ends of the gate electrode; 
 n type semiconductor regions for channel formation formed at side faces of the gate electrode and formed between the source and drain semiconductor regions; and 
 a drain semiconductor region, as the drain, formed in the second surface, 
 
 wherein the N-channel MOSFET comprises:
 a semiconductor substrate of the second semiconductor chip having a first surface and a second surface; 
 a trench formed to extend from the first surface of the semiconductor substrate toward the second surface thereof; 
 a gate insulating film formed over an inner wall surface of the trench; 
 a gate electrode, as the gate, formed over the gate insulating film; 
 n type semiconductor regions, as the source, which are formed in the first surface and formed at both ends of the gate electrode; 
 p type semiconductor regions for channel formation formed at side faces of the gate electrode and formed between the source and drain semiconductor regions; and 
 a drain semiconductor region, as the drain, formed in the second surface. 
 
   
     
     
         11 . A semiconductor device according to  claim 10 ,
 wherein the metal material is comprised of copper.   
     
     
         12 . A semiconductor device according to  claim 10 ,
 wherein the P-channel MOSFET includes a first drain electrode which is electrically coupled to the drain of the first semiconductor chip,   wherein the N-channel MOSFET includes a second drain electrode which is electrically coupled to the drain of the second semiconductor chip, and   wherein the first and second drain electrodes are mechanically coupled to the metal material.   
     
     
         13 . A semiconductor device according to  claim 10 ,
 wherein the resin encapsulator has a top surface and a bottom surface opposite the top surface, and   wherein the input power supply terminal, the reference potential supply terminal and the output terminal are exposed from the bottom surface of the resin body.   
     
     
         14 . A semiconductor device according to  claim 13 ,
 wherein the P-channel MOSFET includes a first source electrode pad which is electrically coupled to the source of the first semiconductor chip,   wherein the N-channel MOSFET includes a second source electrode pad which is electrically coupled to the source of the second semiconductor chip, and   wherein the first and second source electrode pads face toward the top surface of the resin encapsulator.