Resistive random access memory device having nano-scale tip and nanowire, memory array using the same and fabrication method thereof

Abstract

A resistive random access memory device having a nano-scale tip and a nanowire is provided. A memory array using the same also is provided and fabrication method thereof. A technique is provided for forming a bottom electrode having an upwardly protruding tapered tip structure through etching a semiconductor substrate and a top electrode being formed of a nanowire and a technique forming a resistive random access memory device at a location intersected with each other in order that an area of each memory cell is minimized and that an electric field is focused on the tip of the bottom electrode across the top electrode.

What is claimed is: 
     
         1 . A resistive random access memory device comprising:
 a bottom electrode formed in a first direction by etching a semiconductor substrate, the bottom electrode having an upwardly protruding tapered tip structure;   a resistance change layer formed on the bottom electrode; and   a top electrode formed on the resistance change layer in a second direction across the bottom electrode, the top electrode being a nanowire passing over the tip structure.   
     
     
         2 . The resistive random access memory device of  claim 1 , wherein the bottom electrode is wrapped around by an interlayer insulating film except for an upper part of the tip structure, and wherein the resistance change layer is formed on the upper part of the tip structure and the interlayer insulating film. 
     
     
         3 . The resistive random access memory device of  claim 1 , wherein the tip structure has a wedge shape, the wedge shape being configured to have a predetermined length in the first direction and a triangular cross-section in the second direction, and wherein the nanowire is a metal nanowire, a carbon nanotube (CNT) or a grapheme nanoribbon. 
     
     
         4 . The resistive random access memory device of  claim 1 , wherein the tip structure has an upper end size of 10 nm or less in the second direction. 
     
     
         5 . The resistive random access memory device of  claim 2 , wherein the tip structure has an upper end size of 10 nm or less in the second direction. 
     
     
         6 . The resistive random access memory device of  claim 3 , wherein the tip structure has an upper end size of 10 nm or less in the second direction. 
     
     
         7 . A memory array comprising:
 a semiconductor substrate;   a plurality of bit lines formed in a first direction on the semiconductor substrate; and   a plurality of word lines formed in a second direction across the bit lines, a resistance change layer being located between the word lines and the bit lines,   wherein each of the bit lines is formed of a semiconductor line doped with an impurity, the semiconductor line having upwardly protruding tapered tip structures, and   wherein each of the word lines is formed of a nanowire passing over the tip structures of the bit lines along the second direction.   
     
     
         8 . The memory array of  claim 7 , wherein the bit lines are formed in one body with the semiconductor substrate, each of the bit lines being a bottom electrode line doped with an impurity and electrically insulated from adjacent lines with an isolation insulating film, the bottom electrode line having upwardly protruding tapered tip structures along the first direction,
 wherein an interlayer insulating film is further formed between the bit lines and the resistance change layer, the interlayer insulating film wrapping around the tip structures except for upper parts of the tip structures,   wherein the resistance change layer is formed on the upper parts of the tip structures of the each bit line, the interlayer insulating film and the isolation insulating film, and   wherein each of the word lines is formed of a top electrode line passing over the tip structures of the bit lines along the second direction.   
     
     
         9 . The memory array of  claim 7 , wherein the tip structures have a wedge shape, the wedge shape being configured to have a predetermined length in the first direction and a triangular cross-section in the second direction, and wherein the nanowire is a metal nanowire, a carbon nanotube (CNT) or a grapheme nanoribbon. 
     
     
         10 . The memory array of  claim 8 , wherein the tip structures have a wedge shape, the wedge shape being configured to have a predetermined length in the first direction and a triangular cross-section in the second direction, and wherein the nanowire is a metal nanowire, a carbon nanotube (CNT) or a grapheme nanoribbon. 
     
     
         11 . A method for fabricating a memory array, comprising:
 a first step of protruding a plurality of semiconductor lines for forming a plurality of contacts and bit lines by etching a semiconductor substrate;   a second step of forming an isolation insulating film by depositing a first insulating material on the semiconductor substrate and etching the first insulating material to expose upper parts of the semiconductor lines and to be insulated from each other;   a third step of forming protruding patterns on the upper parts of the semiconductor lines;   a fourth step of forming upwardly protruding tapered tip structures from the protruding patterns;   a fifth step of forming a plurality of contacts and bit lines on the upper parts of the semiconductor lines by an ion implantation process;   a sixth step of forming a resistance change layer on the upper parts of the tip structures of the each bit line by depositing a resistance change material, and forming a plurality of contact holes that reach the each contact; and   a seventh step of forming a plurality of word lines with nanowires and forming a plurality of word line contacts and a plurality of bit line contacts filled in the contact holes on the resistance change layer.   
     
     
         12 . The method of  claim 11 , wherein the protruding patterns of the third step have a rectangular shape being formed with a single, and wherein the each word line of the seventh step is formed to be vertically crossed with the each bit line having a wedge shaped tip structure. 
     
     
         13 . The method of  claim 11 , wherein, between the fifth step and the sixth step, it is further including depositing a second insulating material on the upper parts of the plurality of contacts and bits lines and the isolation insulating film and etching the second insulating material and the isolation insulating film to form an interlayer insulating film with the second insulating material, the interlayer insulating film wrapping around the tip structures except for upper parts of the tip structures, wherein the second insulating material is the same as the first insulating material, and wherein the etching process of the second insulating material and the isolation insulating film is performed after a planarization process. 
     
     
         14 . The method of  claim 11 , wherein the each word line of the seventh step is formed by transferring a metal nanowire, a carbon nanotube (CNT) or a graphene nanoribbon. 
     
     
         15 . The method of  claim 11 , wherein the forming of the tip structures of the fourth step is by anisotropically etching the semiconductor lines and/or the protruding patterns. 
     
     
         16 . The method of  claim 15 , wherein the tip structures have an upper end size of 10 nm or less in a vertical direction to the each semiconductor line. 
     
     
         17 . The method of  claim 15 , wherein the protruding patterns of the third step are formed of a semiconductor material. 
     
     
         18 . The method of  claim 15 , wherein the protruding patterns of the third step are etching masks. 
     
     
         19 . The method of  claim 18 , wherein the etching masks are formed by one process selected from photolithography, sidewall patterning and e-beam processes.