Semiconductor Devices and Methods of Manufacturing Thereof

Abstract

In one embodiment, a method of forming a semiconductor device includes forming a first porous semiconductor layer over a top surface of a substrate. A first epitaxial layer is formed over the first porous semiconductor layer. A circuitry is formed within and over the first epitaxial layer. The circuitry is formed without completely oxidizing the first epitaxial layer.

What is claimed is: 
     
         1 . A method of forming a semiconductor device, the method comprising:
 forming a first porous semiconductor layer over a top surface of a substrate;   forming a first epitaxial layer over the first porous semiconductor layer;   forming circuitry within and over the first epitaxial layer, wherein the circuitry is formed without completely oxidizing the first epitaxial layer;   thinning the substrate from a back surface to form a thinned substrate; and   dicing the substrate to form singulated chips, wherein the thinning is stopped before reaching the first porous semiconductor layer.   
     
     
         2 . The method of  claim 1 , wherein the substrate is a silicon wafer. 
     
     
         3 . The method of  claim 1 , wherein forming the first porous semiconductor layer comprises:
 depositing an optional epitaxial layer; and   electrochemically etching at least a portion of the optional epitaxial layer.   
     
     
         4 . The method of  claim 3 , wherein depositing the optional epitaxial layer comprises forming a first layer having a first doping, and a second layer having a second doping different from the first layer. 
     
     
         5 . The method of  claim 1 , wherein forming the first porous semiconductor layer comprises:
 converting a top region of the substrate into the first porous semiconductor layer by etching.   
     
     
         6 . The method of  claim 1 , further comprising forming sublayers within the first porous semiconductor layer by exposing the first porous semiconductor layer to a hydrogen anneal. 
     
     
         7 . The method of  claim 1 , wherein forming a first epitaxial layer comprises exposing the first porous semiconductor layer to a hydrogen anneal. 
     
     
         8 . The method of  claim 1 , wherein the substrate comprises a silicon wafer. 
     
     
         9 . The method of  claim 8 , further comprising forming an epitaxial compound semiconductor layer on the first epitaxial layer. 
     
     
         10 . The method of  claim 9 , wherein the epitaxial compound semiconductor layer comprises a III-V semiconductor. 
     
     
         11 . A method of forming a semiconductor device, the method comprising:
 forming a buffer semiconductor layer having pores or openings over a top surface of a substrate; and   forming a compound semiconductor layer over the buffer semiconductor layer, wherein forming a buffer semiconductor layer comprises:
 patterning a etch mask over the substrate using a lithographic process; and 
 using the etch mask, etching the openings in the substrate. 
   
     
     
         12 . The method of  claim 11 , further comprising forming an epitaxial layer between the buffer semiconductor layer and the compound semiconductor layer. 
     
     
         13 . The method of  claim 11 , further comprising forming circuitry in the compound semiconductor layer. 
     
     
         14 . The method of  claim 13 , wherein the circuitry comprises an optoelectronic device. 
     
     
         15 . The method of  claim 13 , wherein the circuitry comprises a transistor. 
     
     
         16 . The method of  claim 11 , wherein the substrate comprises a silicon wafer, and wherein the compound semiconductor layer comprises GaN. 
     
     
         17 . The method of  claim 11 , wherein the etching is performed using a reactive ion etch process. 
     
     
         18 . The method of  claim 11 , wherein the openings are spaced uniformly on the substrate. 
     
     
         19 . A semiconductor device comprising:
 a first epitaxial layer disposed within a substrate;   circuitry disposed within and over the first epitaxial layer, the circuitry disposed proximate to a top surface of the substrate; and   a first porous layer disposed on a back surface of a substrate, the back surface being opposite to the top surface, wherein the first porous layer comprises a metal silicide.   
     
     
         20 . The device of  claim 19 , further comprising:
 a second porous layer disposed over the first porous layer, the second porous layer comprising porous semiconductor.   
     
     
         21 . The device of  claim 19 , further comprising:
 back side contacts coupled to the first porous layer.   
     
     
         22 . A semiconductor device comprising:
 a buffer semiconductor layer having pores or openings disposed over a top surface of a substrate; and   a compound semiconductor layer disposed over the buffer semiconductor layer.   
     
     
         23 . The device of  claim 22 , wherein the pores or openings are trenches. 
     
     
         24 . The device of  claim 22 , wherein the pores or openings are patterned holes. 
     
     
         25 . The device of  claim 22 , wherein the pores or openings are randomly distributed within the buffer semiconductor layer. 
     
     
         26 . The device of  claim 22 , wherein the substrate comprises a silicon wafer, and wherein the compound semiconductor layer comprises an III-V semiconductor. 
     
     
         27 . The device of  claim 22 , wherein the substrate comprises a silicon wafer, and wherein the compound semiconductor layer comprises GaN. 
     
     
         28 . The device of  claim 22 , further comprising an epitaxial layer disposed between the buffer semiconductor layer and the compound semiconductor layer. 
     
     
         29 . The device of  claim 28 , wherein the substrate comprises a silicon wafer, wherein the epitaxial layer is a silicon layer, and wherein the compound semiconductor layer comprises GaN. 
     
     
         30 . The device of  claim 29 , wherein the GaN is aligned to a (110) surface of the epitaxial layer. 
     
     
         31 . The device of  claim 22 , further comprising device regions disposed in the compound semiconductor layer.