Method of forming metal interconnections of semiconductor device

Abstract

A method of forming a metal interconnection of semiconductor device is provided. The method includes forming a low-k dielectric layer including an opening; forming a barrier metal pattern conformally covering a bottom surface and an inner sidewall of the opening; forming a metal pattern exposing a part of the inner sidewall of the barrier metal pattern in the opening; forming a metal capping layer on the top surfaces of the metal pattern and the low-k dielectric layer using a selective chemical vapor deposition process, wherein the thickness of the metal capping layer on the metal pattern is greater than the thickness of the metal capping layer on the low-k dielectric layer; and forming a metal capping pattern covering the top surface of the metal pattern by planarizing the metal capping layer down to the top surface of the low-k dielectric layer.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a substrate;   a low-k dielectric layer disposed on the substrate and including a trench;   a barrier metal pattern formed in the trench;   a metal pattern formed in the trench and disposed on the barrier metal pattern, the metal pattern being formed of copper;   a metal capping pattern formed in the trench and disposed on the metal pattern; and   a capping insulating layer covering a top surface of the metal capping pattern and a top surface of the low-k dielectric layer,   wherein the capping insulating layer is formed of an insulating material different from the low-k dielectric layer,   a top surface of the metal capping pattern is lower than the top surface of the low-k dielectric layer,   the capping insulating layer includes a first portion disposed on the metal capping pattern and a second portion disposed on the low-k dielectric layer, and   a thickness of at least a part of the first portion of the capping insulating layer is greater than a thickness of at least a part of the second portion of the capping insulating layer.   
     
     
         2 . The semiconductor layer of  claim 1 , further comprising an etch stop layer disposed on the substrate,
 wherein the low-k dielectric layer is disposed on the etch stop layer.   
     
     
         3 . The semiconductor layer of  claim 1 , further comprising an insulating layer disposed on the capping insulating layer. 
     
     
         4 . The semiconductor layer of  claim 1 , wherein the barrier metal pattern is disposed on sidewalls of the trench and on a bottom of the trench. 
     
     
         5 . The semiconductor layer of  claim 1 , wherein the metal pattern directly contacts sidewalls of the barrier metal pattern. 
     
     
         6 . The semiconductor layer of  claim 1 , wherein the metal capping pattern directly contacts sidewalls of the barrier metal pattern. 
     
     
         7 . The semiconductor layer of  claim 1 , wherein the capping insulating layer directly contacts sidewalls of the barrier metal pattern. 
     
     
         8 . The semiconductor layer of  claim 1 , wherein the metal capping pattern includes ruthenium. 
     
     
         9 . The semiconductor layer of  claim 1 , wherein a thickness of the first portion of the capping insulating layer is greater than a thickness of the second portion of the capping insulating layer. 
     
     
         10 . A semiconductor device comprising:
 a substrate;   a low-k dielectric layer disposed on the substrate and including a trench;   a barrier metal pattern formed in the trench;   a metal pattern formed in the trench and disposed on the barrier metal pattern, the metal pattern being formed of copper;   a metal capping pattern formed in the trench and disposed on the metal pattern; and   a capping insulating layer covering a top surface of the metal capping pattern and a top surface of the low-k dielectric layer,   wherein the capping insulating layer is formed of an insulating material different from the low-k dielectric layer,   a top surface of the metal capping pattern is lower than the top surface of the low-k dielectric layer,   the capping insulating layer includes a first portion and a second portion, and   a thickness of the first portion of the capping insulating layer is greater than a thickness of the second portion of the capping insulating layer.   
     
     
         11 . The semiconductor layer of  claim 10 , wherein the first portion of the capping insulating layer is disposed on the metal capping pattern, and
 the second portion of the capping insulating layer is disposed on the low-k dielectric layer.   
     
     
         12 . The semiconductor layer of  claim 10 , wherein the barrier metal pattern is disposed on sidewalls of the trench and on a bottom of the trench. 
     
     
         13 . The semiconductor layer of  claim 10 , wherein the metal pattern directly contacts sidewalls of the barrier metal pattern. 
     
     
         14 . The semiconductor layer of  claim 10 , wherein the metal capping pattern directly contacts sidewalls of the barrier metal pattern. 
     
     
         15 . The semiconductor layer of  claim 10 , wherein the capping insulating layer directly contacts sidewalls of the barrier metal pattern. 
     
     
         16 . A semiconductor device comprising:
 a low-k dielectric layer including a trench;   a barrier metal pattern formed in the trench;   a metal pattern formed in the trench and disposed on the barrier metal pattern;   a metal capping pattern formed in the trench and disposed on the metal pattern; and   a capping insulating layer covering a top surface of the metal capping pattern and a top surface of the low-k dielectric layer,   wherein a top surface of the metal capping pattern is lower than the top surface of the low-k dielectric layer,   the capping insulating layer includes a first portion disposed on the metal capping pattern and a second portion disposed on the low-k dielectric layer, and   a thickness of the first portion of the capping insulating layer is different from a thickness of the second portion of the capping insulating layer.   
     
     
         17 . The semiconductor layer of  claim 16 , wherein the thickness of the first portion of the capping insulating layer is greater than the thickness of the second portion of the capping insulating layer. 
     
     
         18 . The semiconductor layer of  claim 16 , wherein the capping insulating layer is formed of an insulating material different from the low-k dielectric layer. 
     
     
         19 . The semiconductor layer of  claim 16 , wherein the metal pattern includes copper, and
 the metal capping pattern includes ruthenium.   
     
     
         20 . The semiconductor layer of  claim 16 , wherein the barrier metal pattern is disposed on sidewalls of the trench and on a bottom of the trench.