Level shift circuit and semiconductor device

Abstract

A level shift circuit includes: a latch circuit (Q 5 , Q 6 , Q 7 , Q 8 ) including first (Q 5 , Q 7 ) and second (Q 6 , Q 8 ) inverter circuits; a first input MOS transistor (Q 1 ) operating in accordance with an input signal; a second input MOS transistor (Q 2 ) operating in accordance with an inversion signal of the input signal; and a current-voltage control MOS transistor (Q 9 ). The latch circuit (Q 5 , Q 6 , Q 7 , Q 8 ) outputs a voltage having been converted from the input voltage in level. Each of the first and second input MOS transistors (Q 1 , Q 2 ) receives the input signal at its gate terminal, and drives the latch circuit (Q 5 , Q 6 , Q 7 , Q 8 ) in accordance with the input signal. The current-voltage control MOS transistor (Q 9 ) is provided between the input MOS transistor (Q 1 , Q 2 ) and the latch circuit (Q 5 , Q 6 , Q 7 , Q 8 ), and is driven in accordance with an inversion operation of the latch circuit by receiving an input of the control voltage at its gate terminal.

1 . A level shift circuit comprising:
 a latch circuit fed with an operation voltage;   a first MOS transistor for receiving an input signal at its gate terminal to drive the latch circuit;   a second MOS transistor for receiving an inversion signal of the input signal at its gate terminal to drive the latch circuit;   a third MOS transistor, provided between the latch circuit and the first MOS transistor, for receiving a first control voltage at its gate terminal to operate to open/close;   a fourth MOS transistor, provided between the latch circuit and the second MOS transistor, for receiving the first control voltage at its gate terminal to operate to open/close; and   a current-voltage control MOS transistor, connected to the latch circuit, for receiving a second control voltage at its gate terminal,   the current-voltage control MOS transistor being turned off during an inversion operation based on the input signal.   
     
     
         2 . The level shift circuit according to  claim 1 , wherein
 the latch circuit includes
 a first inverter circuit, and 
 a second inverter circuit, and 
   the first inverter circuit and the second inverter circuit have input and output terminals cross-coupled to each other.   
     
     
         3 . The level shift circuit according to  claim 2 , wherein
 the current-voltage control MOS transistor and the latch circuit are connected to each other via a node,   the first inverter circuit includes fifth and seventh MOS transistors connected in series between the node and a first voltage terminal fed with the operation voltage, and   the second inverter circuit includes sixth and eighth MOS transistors connected in series between the first voltage terminal and the node.   
     
     
         4 . The level shift circuit according to  claim 2 , wherein
 the current-voltage control MOS transistor includes a ninth MOS transistor and a tenth MOS transistor,   the tenth MOS transistor and the latch circuit are connected to each other via a first node,   the ninth MOS transistor and the latch circuit are connected to each other via a second node,   the first inverter circuit includes fifth and seventh MOS transistors connected in series between the first node and a first voltage terminal fed with the operation voltage,   the second inverter circuit includes sixth and eighth MOS transistors connected in series between the first voltage terminal and the second node,   the first inverter circuit includes a thirteenth MOS transistor provided to be connected in series between the fifth and seventh MOS transistors and having a gate terminal connected to the second node, and   the second inverter circuit includes a fourteenth MOS transistor provided to be connected in series between the sixth and eighth MOS transistors and having a gate terminal connected to the first node,   the level shift circuit further comprising:   an eleventh MOS transistor for receiving the input signal at its gate terminal, the eleventh MOS transistor being connected to the latch circuit via the first node; and   a twelfth MOS transistor for receiving an inversion signal of the input signal at its gate terminal, the twelfth MOS transistor being connected to the latch circuit via the second node.   
     
     
         5 . A level shift circuit comprising:
 a latch circuit fed with an operation voltage;   a first MOS transistor for receiving an input signal at its gate terminal to drive the latch circuit;   a second MOS transistor for receiving an inversion signal of the input signal at its gate terminal to drive the latch circuit;   third and fourth MOS transistors, provided to divide two inverter circuits included in the latch circuit, each for receiving a first control voltage at its gate terminal to operate to open/close; and   a current-voltage control MOS transistor, connected to the latch circuit, for receiving a second control voltage at its gate terminal,   the current-voltage control MOS transistor being turned off during an inversion operation based on the input signal.   
     
     
         6 . A level shift circuit according to  claim 5 , wherein
 the latch circuit includes
 a first inverter circuit, and 
 a second inverter circuit, 
   the first inverter circuit and the second inverter circuit have input and output terminals cross-coupled to each other,   the current-voltage control MOS transistor and the latch circuit are connected to each other via a node,   the first inverter circuit includes fifth and seventh MOS transistors connected in series between the node and a first voltage terminal fed with the operation voltage,   the second inverter circuit includes sixth and eighth MOS transistors connected in series between the first voltage terminal and the node,   the third MOS transistor is provided to be connected in series between the fifth and seventh MOS transistors, and   the fourth MOS transistor is provided to be connected in series between the sixth and eighth MOS transistors.   
     
     
         7 . The level shift circuit according to  claim 5 , wherein
 the latch circuit includes
 a first inverter circuit, and 
 a second inverter circuit, 
   the first inverter circuit and the second inverter circuit have input and output terminals cross-coupled to each other,   the current-voltage control MOS transistor includes a ninth MOS transistor and a tenth MOS transistor,   the tenth MOS transistor and the latch circuit are connected to each other via a first node,   the ninth MOS transistor and the latch circuit are connected to each other via a second node,   the first inverter circuit includes fifth and seventh MOS transistors connected in series between the first node and a first voltage terminal fed with the operation voltage,   the second inverter circuit includes sixth and eighth MOS transistors connected in series between the first voltage terminal and the second node,   the third MOS transistor is provided to be connected in series between the fifth and seventh MOS transistors,   the fourth MOS transistor is provided to be connected in series between the sixth and eighth MOS transistors,   the first inverter circuit includes a thirteenth MOS transistor provided to be connected in series between the fifth and seventh MOS transistors and having a gate terminal connected to the second node, and   the second inverter circuit includes a fourteenth MOS transistor provided to be connected in series between the sixth and eighth MOS transistors and having a gate terminal connected to the first node,   the level shift circuit further comprising:   an eleventh MOS transistor for receiving the input signal at its gate terminal, the eleventh MOS transistor being connected to the latch circuit via the first node; and   a twelfth MOS transistor for receiving an inversion signal of the input signal at its gate terminal, the twelfth MOS transistor being connected to the latch circuit via the second node.