Suspended body field effect transistor

Abstract

A semiconductor fin including a vertical stack, from bottom to top, of a second semiconductor material and a first semiconductor material is formed on a substrate. A disposable gate structure straddling the semiconductor fin is formed. A source region and a drain region are formed employing the disposable gate structure as an implantation mask, At least one semiconductor shell layer or a semiconductor cap layer can be formed as an etch stop structure. A planarization dielectric layer is subsequently formed. A gate cavity is formed by removing the disposable gate structure. A portion of the second semiconductor material is removed selective to the first semiconductor material within the gate cavity so that a middle portion of the semiconductor fin becomes suspended over the substrate. A gate dielectric layer and a gate electrode are sequentially formed. The gate electrode laterally surrounds a body region of a fin field effect transistor.

1 .- 10 . (canceled) 
     
     
         11 . A method of forming a semiconductor structure comprising:
 forming a vertical stack, from bottom to top, of a buffer semiconductor portion and a semiconductor fin on a substrate, wherein said buffer semiconductor portion comprises a buffer semiconductor material and said semiconductor fin comprises a semiconductor material different from said buffer semiconductor material;   forming a disposable gate structure straddling said vertical stack;   forming a planarization dielectric layer over said vertical stack, wherein a top surface of said planarization dielectric layer is coplanar with a top surface of said disposable gate structure;   forming a gate cavity by removing said disposable gate structure;   laterally extending said gate cavity by removing a physically exposed portion of said buffer semiconductor portion, wherein a region of said semiconductor fin becomes suspended within said gate cavity.   forming a gate dielectric layer and a gate electrode within said gate cavity.   
     
     
         12 . The method of  claim 11 , further comprising forming a source region and drain region within said semiconductor fin by implanting dopant atoms employing said disposable gate structure as an implantation mask. 
     
     
         13 . The method of claim  1 , further comprising:
 forming at least one semiconductor shell layer directly on sidewalls of said semiconductor fin; and   removing a physically exposed portion of said at least one semiconductor shell layer within said gate cavity prior to formation of said gate dielectric layer.   
     
     
         14 . The method of  claim 13 , wherein said at least one semiconductor shell layer comprises:
 a first semiconductor shell layer deposited directly on sidewalls surfaces of said semiconductor fin and said buffer semiconductor portion; and   a second semiconductor shell layer deposited directly on surfaces of said first semiconductor shell layer.   
     
     
         15 . The method of  claim 13 , wherein said gate dielectric layer is formed directly on sidewalls surfaces of remaining portions of said first and second semiconductor shell layers. 
     
     
         16 . The method of  claim 13 , wherein said first semiconductor shell layer comprises a same material as said buffer semiconductor portion, and said second semiconductor shell layer comprises a semiconductor material having a greater conductivity than said first semiconductor material as provided upon formation of said vertical stack. 
     
     
         17 . The method of  claim 11 , wherein remaining portions of said buffer semiconductor portion comprise:
 a first buffer semiconductor portion in contact with a first portion of a top surface of said substrate and a bottom surface of said source region; and   a second buffer semiconductor portion in contact with a second portion of said top surface of said substrate and a bottom surface of said drain region.   
     
     
         18 . The method of  claim 11 , wherein said vertical stack further comprises a cap semiconductor portion in contact with a top surface of said semiconductor fin. 
     
     
         19 . The method of  claim 16 , wherein said gate electrode laterally surrounds said suspended portion of said semiconductor fin. 
     
     
         20 . The method of  claim 11 , further comprising:
 removing said planarization dielectric layer after formation of said gate electrode; and   forming a raised source region and a raised drain region on sidewalls of remaining portions of said buffer semiconductor portion and sidewalls of said semiconductor fin.   
     
     
         21 . The method of  claim 18 , wherein said laterally extending said gate cavity further comprises removing a physically exposed portion of said cap semiconductor portion within said gate cavity. 
     
     
         22 . The method of  claim 18 , wherein said cap semiconductor portion comprises a semiconductor material the same as said buffer semiconductor material. 
     
     
         23 . The method of  claim 22 , wherein said physically exposed portions of said cap semiconductor portion and said buffer semiconductor portion are removed by a crystallographic-orientation dependent etch. 
     
     
         24 . The method of  claim 12 , further comprising forming contact via structures extending through said planarization dielectric layer and contacting said source region and said drain region.