Method for making an integrated circuit

Abstract

A method includes making a gate stack on the surface of an active zone, including depositing a first dielectric layer; depositing a gate conductive layer; depositing a first metal layer; depositing a second metal layer; depositing a second dielectric layer; partially etching the gate stack for the formation of a gate zone on the active zone; making insulating spacers on either side of the gate zone on the active zone; making source and drain electrodes zones; making silicidation zones on the surface of the source and drain zones; etching, in the gate zone on the active zone, the second dielectric layer and the second metal layer with stopping on the first metal layer, so as to form a cavity between the insulating spacers; making a protective plug at the surface of the first metal layer of the gate zone on the active zone, where the protective plug fills the cavity.

1 .- 15 . (canceled) 
     
     
         16 . An integrated circuit comprising:
 an active zone and an insulation zone;   a gate zone on the active zone, comprising a layer of a first dielectric, a gate conductive layer, a layer of a first metal and a protective plug;   a gate zone on the insulation zone, comprising a layer of a first dielectric, a gate conductive layer, a layer of a first metal and a layer of a second metal;   
     
     
         17 . The integrated circuit according to  claim 16 , wherein the layer of the first metal is a layer made of an alloy of refractory metal. 
     
     
         18 . The integrated circuit according to  claim 17 , wherein the layer of the first metal is a layer of one of the following materials:
 an alloy of Titanium Ti;   an alloy of Tungsten W;   an alloy of Tantalum Ta;   an alloy of a metal and silicon Si;   
     
     
         19 . The integrated circuit according to  claim 16 , wherein the layer of the second metal is a layer made of an alloy of refractory metal. 
     
     
         20 . The integrated circuit according to  claim 19 , wherein the layer of the second metal is a layer of one of the following materials:
 an alloy of Titanium Ti;   an alloy of Tungsten W;   an alloy of Tantalum Ta;   
     
     
         21 . The integrated circuit according to  claim 16 , wherein the first metal in the layer of the first metal is different from the second metal in the layer of the second metal. 
     
     
         22 . The integrated circuit according to  claim 21 , wherein the layer of the second metal may be selectively etched in relation to the layer of the first metal. 
     
     
         23 . The integrated circuit according to  claim 22 , wherein the etching selectivity ratio between the layer of the second metal and the layer of the first metal is greater than 5:1. 
     
     
         24 . The integrated circuit according to  claim 16 , wherein the layer of the first metal has a thickness greater than or equal to 15 nm. 
     
     
         25 . The integrated circuit according to  claim 16 , wherein the layer of the second metal has a thickness of between 20 nm and 50 nm. 
     
     
         26 . The integrated circuit according to  claim 16 , wherein the gate conductive layer has a thickness greater than or equal to 15 nm. 
     
     
         27 . The integrated circuit according to  claim 16 , wherein a cumulative thickness of the gate conductive layer and of the layer of the first metal is less than or equal to 100 nm. 
     
     
         28 . The integrated circuit according to  claim 16 , comprising a conductive material on active zone, on source and drain silicidation zones on either side of the gate zone on active zone; the circuit between the drain and source silicidation zones being broken. 
     
     
         29 . The integrated circuit according to  claim 16 , comprising:
 on the source and drain silicidation zones, source and drain contacts made of a conductive material which are self-aligned on the gate zone on the active zone;   a gate contact on insulation zone made from a conductive material, wherein the gate contact is in direct contact with the layer of second metal of the gate zone on insulation zone.   
     
     
         30 . The integrated circuit according to  claim 16 , wherein the dielectric plug is made of a dielectric material including silicon nitride SiN, boron nitride BN or hafnium oxide HfO 2 .