Methods, apparatus and system for reduction of power consumption in a semiconductor device

Abstract

At least one method, apparatus and system disclosed herein involves performing power reduction process on a FinFET device. A first design is provided. The first design comprises a process mask definition, a FinFET device that comprises a plurality of fins characterized by said process mask, and a timing requirement relating to an operation of said FinFET device. A timing parameter of said operation of said FinFET device is determined. Based upon said timing parameter, a determination is made as to whether a drive capability of said FinFET device is above a level required to maintain said timing requirement. The process mask is modified for reducing at least one of said fins in response to said determining that said drive capability is above said level required to maintain said timing requirement.

1 - 20 . (canceled) 
     
     
         21 . A FinFET device, comprising:
 a semiconductor substrate;   a plurality of active fins disposed on the semiconductor substrate, wherein a distance between at least one pair of adjacent active fins is based on a timing requirement relating to an operation of the FinFET device;   a diffusion layer disposed between each pair of adjacent active fins of the plurality of active fins;   a gate portion in contact with the plurality of active fins;   a source portion in contact with the plurality of active fins; and   a drain portion in contact with the plurality of active fins;   wherein a P-channel transistor comprises a first subset of the plurality of active fins and an N-channel transistor comprises a second subset of the plurality of active fins.   
     
     
         22 . The FinFET device of  claim 21 , wherein the first subset and the second subset each comprise seven active fins. 
     
     
         23 . The FinFET device of  claim 21 , wherein the first subset and the second subset each comprise four active fins. 
     
     
         24 . The FinFET device of  claim 21 , wherein the first subset and the second subset each comprise three active fins. 
     
     
         25 . A FinFET device, comprising:
 a semiconductor substrate;   a plurality of active fins disposed on the semiconductor substrate, wherein a distance between at least one pair of adjacent active fins is based on a timing requirement relating to an operation of the FinFET device;   a dummy fin disposed on the semiconductor substrate between a first subset of the plurality of active fins and a second subset of the plurality of active fins;   a diffusion layer disposed between each pair of adjacent active fins of the plurality of active fins;   a first gate portion in contact with the first subset of the plurality of active fins;   a second gate portion in contact with the second subset of the plurality of active fins;   a first source portion in contact with the first subset of the plurality of active fins;   a second source portion in contact with the second subset of the plurality of active fins;   a first drain portion in contact with the first subset of the plurality of active fins; and   a second drain portion in contact with the second subset of the plurality of active fins;   wherein a P-channel transistor comprises the first subset of the plurality of active fins and an N-channel transistor comprises the second subset of the plurality of active fins.   
     
     
         26 . The FinFET device of  claim 25 , wherein the first subset and the second subset each comprise seven active fins. 
     
     
         27 . The FinFET device of  claim 25 , wherein the first subset and the second subset each comprise four active fins. 
     
     
         28 . The FinFET device of  claim 25 , wherein the first subset and the second subset each comprise three active fins.