Digital-to-analog-conversion circuit and data driver for display device

Abstract

DAC includes a decoder that receives N number of reference voltages and an n-bit digital signal (n 4) to select first to third voltages, and an operational amplifier to output (first voltage+second voltage+2 third voltage)/4 voltage. The operational amplifier is able to output, for respective 2̂n combinations of the n-bit digital signal, voltage levels from an Ath level, as a base level, to an (A−1+2̂n)th level. The N number of reference voltages include Ath level, (A+4)th level, (A−4+2̂n) and (A+2̂n), and an at most {−4+2̂(n−2)} reference voltages obtained by decimating a pre-set at least one reference voltage from {−3+2̂(n−2)} reference voltages that are other than the four number of reference voltages from the {1+2̂(n−2)} reference voltages corresponding to the voltage levels spaced each other at an interval of 4 levels from the Ath level. N is not less than 4 and not more than 2̂(n−2).

What is claimed is: 
     
         1 . A driver circuit for a display device, comprising:
 a first decoder that receives first to N-th reference voltages and an n-bit digital signal (n being a predetermined integer not less than 4) and outputs first to third voltages selected from the first to N-th reference voltages in accordance with the n-bit digital signal; and   an operational amplifier that receives the first to third voltages and outputs a voltage level corresponding to a summation of the first voltage, the second voltage and a double of the third voltage, wherein   among first to (2̂n+1)-th voltage levels output by the operational amplifier,   the first, fifth, (2̂n−3)-th, and the (2̂n+1)-th voltage levels correspond respectively to the first, second, (N−1)-th and the N-th reference voltages, and   voltage levels between the first to (2̂n+1)-th voltage levels are equally spaced, and wherein N is an integer not less than 4 and not more than 2 ̂ ̂(n−2).   
     
     
         2 . The driver circuit according to  claim 1 , wherein
 voltage levels of the reference voltages placed between the second reference voltage and the (N−1)-th reference voltage are equally spaced, and wherein N is an integer not less than 5 and not more than 2 ̂ ̂(n−2), wherein n is a predetermined integer not less than 5.   
     
     
         3 . The driver circuit according to  claim 1 , wherein
 voltage levels of reference voltages placed between the second reference voltage and the (N−1)-th reference voltage are equally spaced, wherein N is an integer not less than 6 and not more than 2 ̂ ̂(n−2), and wherein n is a predetermined integer not less than 5.   
     
     
         4 . The driver circuit according to  claim 1 , wherein
 voltage levels of reference voltages between the third reference voltage and the (N−2)-th reference voltage are equally spaced, wherein N is an integer not less than 7 and not more than 2 ̂ ̂(n−2), and wherein n is a predetermined integer not less than 6.   
     
     
         5 . The driver circuit according to  claim 4 , wherein
 a difference between voltage levels of the second and third reference voltages is equal to a difference between voltage levels of the (N−2)-th and (N−1)-th reference voltages.   
     
     
         6 . A display device including:
 a pixel switch; and   a display element at an intersection of a data line and a scan line,   a signal on the data line being written on the display element via the pixel switch turned on by the scan line, wherein   the display device includes   a data driver that drives the data line, the data driver including the driver circuit as set forth in  claim 1 .   
     
     
         7 . The display device according to  claim 6 , wherein
 the display element is a liquid crystal element or an organic LED.