Efficient Memory Architecture for Low Density Parity Check Decoding

Abstract

A low density parity check (LDPC) decoder integrated on a single semiconductor substrate may comprise one or more arrays of first-type memory cells and one or more arrays of second-type memory cells. The LDPC decoder may be configured to store intrinsic messages in the array of first-type cells and to store extrinsic messages in the array of second-type cells. The first-type cells may be a first one of: static random access memory (SRAM) cells, refreshed dynamic random access memory (DRAM) cells, non-refreshed DRAM cells configured as a FIFO, and non-refreshed DRAM cells not configured as a FIFO. The second-type cells may be a second one of: static random access memory (SRAM) cells, refreshed dynamic random access memory (DRAM) cells, non-refreshed DRAM cells configured as a FIFO, and non-refreshed DRAM cells not configured as a FIFO.

1 - 20 . (canceled) 
     
     
         21 . A system comprising:
 a low density parity check (LDPC) decoder comprising one or more arrays of static random access memory (SRAM) cells and one or more arrays of dynamic random access memory (DRAM) cells, wherein said LDPC decoder is configured to:   store data which is overwritten at a rate that is greater than a determined threshold rate to said DRAM, and   data which is overwritten at a rate that is less than said determined threshold rate to said SRAM.   
     
     
         22 . The system of  claim 21 , wherein each of said DRAM cells is a one-transistor (“1T”) DRAM cell. 
     
     
         23 . The system of  claim 21 , wherein said one or more arrays of DRAM cells comprises one or more arrays of non-refreshed DRAM (NDRAM) cells, each of which neither comprises, nor is coupled to, memory refresh circuitry. 
     
     
         24 . The system of  claim 21 , wherein said one or more arrays of NDRAM cells are used for edge memory and accumulate and extension memory of said LDPC decoder. 
     
     
         25 . The system of  claim 23 , wherein said one or more arrays of DRAM cells comprise an array of refreshed DRAM cells which comprises and/or is coupled to memory refresh circuitry. 
     
     
         26 . The system of  claim 21 , wherein each of said SRAM cells is a six-transistor (“6T”) SRAM cell. 
     
     
         27 . The system of  claim 21 , wherein:
 said DRAM cells are cells of a same semiconductor device fabrication process as said SRAM cells; and   said DRAM cells adhere to a same set of design rules as said SRAM cells.   
     
     
         28 . The system of  claim 21 , comprising a deinterleaver is integrated on a semiconductor substrate with said LDPC decoder, wherein said deinterleaver is configured to store bits being deinterleaved in said one or more arrays of SRAM cells. 
     
     
         29 . The system of  claim 21 , wherein:
 a first array of said one or more arrays of DRAM cells is configured as a shift register and a second array of said one or more arrays of DRAM cells is not configured as a shift register;   said first array is used for storage of data which is overwritten at greater than a threshold rate; and   said second array is used for storage of data which is overwritten at less than said threshold rate.   
     
     
         30 . The system of  claim 21 , wherein different cells of said one or more arrays of DRAM cells are sized differently according to different rates at which data stored in said different cells is overwritten.