Semiconductor device

Abstract

A semiconductor device capable of accurately controlling the cycle of an internal clock signal. This semiconductor device, by using signal that is output from a sequence register of an asynchronous successive approximation type ADC when N times of comparison are completed, detects whether or not the signal and its delay signal are output when the period transitions from a comparison period to a sampling period, and generates, on the basis of the detection result, a delay control signal for controlling the cycle of an internal clock signal by controlling the delay times of the delay circuits.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 an asynchronous successive approximation type Analog-to-Digital (A/D) converter that samples an external analog signal in a sampling period, generates an internal clock signal in a comparison period, performs comparisons in synchronization with the internal clock signal, and converts the external analog signal to an n-bit digital signal where n is an integer equal to or greater than 2 on the basis of a comparison result; and   a control circuit that detects whether the conversion from the external analog signal to an n-th digital signal is completed or not when a period transitions from the comparison period to the sampling period, and that controls a cycle of the internal clock signal on the basis of a detection result.   
     
     
         2 . The semiconductor device according to  claim 1 ,
 wherein the asynchronous successive approximation type A/D converter performs first to n-th comparisons in synchronization with first to n-th leading edges of the internal clock signal,   wherein the asynchronous successive approximation type A/D converter includes a sequence register that outputs first to n-th signals indicating that the first to n-th comparisons have been performed, respectively,   the semiconductor device further comprising a control circuit that detects whether or not the n-th signal is output when a period transitions from the comparison period to the sampling period, and that controls a cycle of the internal clock signal on the basis of a detection result.   
     
     
         3 . The semiconductor device according to  claim 2 , further comprising a delay circuit that delays the n-th signal and generates an (n+1)th signal,
 wherein the control circuit detects whether or not the n-th and (n+1)th signals are output, respectively, when a period transitions from the comparison period to the sampling period, and controls a cycle of the internal clock signal on the basis of a detection result.   
     
     
         4 . The semiconductor device according to  claim 3 ,
 wherein the control circuit:
 reduces a cycle of the internal clock signal when both the n-th and (n+1)th signals are not output, 
 increases the cycle of the internal clock signal when both the n-th and (n+1)th signals are output, and 
 maintains the cycle of the internal clock signal when the first signal is output and prior to the second signal being output. 
   
     
     
         5 . The semiconductor device according to  claim 2 , further comprising a plurality of delay circuits that is coupled in series and that delays the n-th signal,
 wherein the control circuit detects, when a period transitions from the comparison period to the sampling period, whether or not the n-th signal and an output signal of the delay circuits are output, respectively, and controls a cycle of the internal clock signal on the basis of a detection result.   
     
     
         6 . The semiconductor device according to  claim 2 , wherein the control circuit:
 reduces a cycle of the internal clock signal when the n-th signal is not output yet, and increases a cycle of the internal clock signal when the n-th signal is output.   
     
     
         7 . The semiconductor device according to  claim 2 ,
 wherein the n-th comparison is a preliminary comparison, and   wherein the asynchronous successive approximation type A/D converter converts the external analog signal to an (n−1) bit digital signal.   
     
     
         8 . The semiconductor device according to  claim 2 ,
 wherein the asynchronous successive approximation type A/D converter includes an internal clock generation circuit that includes a delay circuit capable of controlling a delay time, generates an internal clock signal of a cycle corresponding to the delay time in accordance with transition from the sampling period to the comparison period, and stops generation of the internal clock signal in response to the n-th signal, and   wherein the control circuit controls a delay time of the delay circuit to control a cycle of the internal clock signal.   
     
     
         9 . The semiconductor device according to  claim 8 ,
 wherein the control circuit generates a delay control signal of a thermometer format for controlling the delay time, and   wherein the delay time varies depending on the delay control signal of the thermometer format.   
     
     
         10 . The semiconductor device according to  claim 8 ,
 wherein the control circuit generates a delay control signal of a binary format for controlling the delay time, and   wherein the delay time varies depending on a delay control signal of the binary format.   
     
     
         11 . The semiconductor device according to  claim 10 ,
 wherein a change amount of the delay time differs for each bit of the delay control signal of the binary format.   
     
     
         12 . The semiconductor device according to  claim 8 ,
 wherein the control circuit generates a delay control signal of a binary format for controlling the delay time, and further includes a decoder that converts the delay control signal of the binary format to a delay control signal of a thermometer format, and   wherein the delay time varies depending on the delay control signal of the thermometer format.   
     
     
         13 . The semiconductor device according to  claim 2 ,
 wherein the sampling period is a period during which the external clock signal is at a first logic level, and   wherein the comparison period is a period during which the external clock signal is at a second logic level.