Finfet semiconductor device with isolated channel regions

Abstract

A FinFET device includes a fin structure positioned in the channel region of the device and a gate structure positioned above the fin structure, wherein the fin structure includes a portion of a semiconductor substrate and an epi semiconductor material positioned vertically above the portion of the semiconductor substrate. Sidewall spacers are positioned adjacent the gate structure and a fin cavity is positioned in source/drain regions of the device, wherein the fin structure has edges in a gate width direction that are substantially self-aligned with the sidewall spacers and the semiconductor substrate defines the bottom of the fin cavity. A silicon etch stop layer is positioned on and in contact with the edges of the fin structure and within the fin cavity, and a stressed semiconductor material is positioned on and in contact with the silicon etch stop layer and at least partially within the fin cavity.

What is claimed: 
     
         1 . A FinFET device, comprising:
 a fin structure positioned in a channel region of said FinFET device, wherein said fin structure comprises:
 a portion of a semiconductor substrate; and 
 an epi semiconductor material positioned vertically above said portion of said semiconductor substrate; 
   a gate structure positioned above said fin structure in said channel region of said FinFET device;   sidewall spacers positioned adjacent said gate structure, wherein said fin structure has edges in a gate width direction of said FinFET device that are substantially self-aligned with said sidewall spacers;   a fin cavity positioned in source/drain regions of said FinFET device, wherein said semiconductor substrate defines a bottom of said fin cavity;   a silicon etch stop layer positioned on and in contact with said edges of said fin structure and within said fin cavity; and   a stressed semiconductor material positioned on and in contact with said silicon etch stop layer and at least partially within said fin cavity.   
     
     
         2 . The FinFET device of  claim 1 , wherein said silicon etch stop layer is positioned on said bottom of said fin cavity and on sidewalls of said fin cavity. 
     
     
         3 . The FinFET device of  claim 1 , wherein said stressed semiconductor material is silicon-germanium (Si x Ge 1-x ). 
     
     
         4 . The FinFET device of  claim 1 , wherein said gate structure comprises a gate insulation layer and a gate electrode positioned on said gate insulation layer, said gate insulation layer comprising a high-k insulating material and said gate electrode comprising at least one layer of metal. 
     
     
         5 . The FinFET device of  claim 1 , further comprising a gate cap layer positioned above said gate structure. 
     
     
         6 . The FinFET device of  claim 5 , wherein said sidewall spacers are positioned adjacent and laterally confine said gate cap layer. 
     
     
         7 . The FinFET device of  claim 1 , wherein said silicon etch stop layer covers said semiconductor substrate portion of said fin structure and said epi semiconductor material of said fin structure along at least said edges of said fin structure. 
     
     
         8 . A FinFET device, comprising:
 a fin structure positioned in a channel region of said FinFET device, wherein said fin structure comprises:
 a portion of a semiconductor substrate; and 
 an epi semiconductor material positioned vertically above said portion of said semiconductor substrate; 
   a gate structure positioned above said fin structure in said channel region of said FinFET device, wherein said gate structure comprises a gate insulation layer and a gate electrode, said gate insulation layer comprising a high-k insulating material and said gate electrode comprising at least one layer of metal;   sidewall spacers positioned adjacent said gate structure, wherein said fin structure has edges in a gate width direction of said FinFET device that are substantially self-aligned with said sidewall spacers;   a fin cavity positioned in source/drain regions of said FinFET device, wherein said semiconductor substrate defines a bottom of said fin cavity;   a silicon etch stop layer positioned on and in contact with said edges of said fin structure, on said bottom of said fin cavity, and on sidewalls of said fin cavity; and   a stressed semiconductor material positioned on and in contact with said silicon etch stop layer and at least partially within said fin cavity.   
     
     
         9 . The FinFET device of  claim 8 , wherein said high-k insulating material has a dielectric constant of approximately 10 or greater and said at least one layer of metal comprises a plurality of metal layers. 
     
     
         10 . The FinFET device of  claim 8 , wherein said gate electrode further comprises a layer of conductive material positioned above said at least one layer of metal. 
     
     
         11 . The FinFET device of  claim 8 , further comprising a gate cap layer positioned above said gate structure, wherein said sidewall spacers are positioned adjacent and laterally confine said gate cap layer. 
     
     
         12 . The FinFET device of  claim 8 , wherein said silicon etch stop layer covers said semiconductor substrate portion of said fin structure and said epi semiconductor material of said fin structure along sidewalls and said edges of said fin structure. 
     
     
         13 . A FinFET device, comprising:
 a fin structure positioned in a channel region of said FinFET device, wherein said fin structure comprises:
 a portion of a semiconductor substrate; 
 an epi semiconductor material positioned vertically above said portion of said semiconductor substrate; 
   a gate structure positioned above said fin structure in said channel region of said FinFET device;   sidewall spacers positioned adjacent said gate structure, wherein said fin structure has edges in a gate width direction of said FinFET device that are substantially self-aligned with said sidewall spacers;   a fin cavity positioned in source/drain regions of said FinFET device, wherein said semiconductor substrate defines a bottom of said fin cavity;   a silicon etch stop layer positioned on and in contact with said edges of said fin structure, on said bottom of said fin cavity, and on sidewalls of said fin cavity, said silicon etch stop layer covering said semiconductor substrate portion of said fin structure and said epi semiconductor material of said fin structure along at least said edges of said fin structure; and   a stressed semiconductor material positioned on and in contact with said silicon etch stop layer and at least partially within said fin cavity, said stressed semiconductor material comprising silicon-germanium (Si x Ge 1-x ).   
     
     
         14 . The FinFET device of  claim 13 , wherein said gate structure comprises a gate insulation layer and a gate electrode positioned on said gate insulation layer. 
     
     
         15 . The FinFET device of  claim 14 , wherein said gate insulation layer comprises a high-k insulating material, and wherein said gate electrode comprises at least one layer of metal. 
     
     
         16 . The FinFET device of  claim 15 , wherein said high-k insulating material has a dielectric constant of approximately 10 or greater. 
     
     
         17 . The FinFET device of  claim 15 , wherein said at least one layer of metal comprises a plurality of metal layers. 
     
     
         18 . The FinFET device of  claim 15 , wherein said gate electrode further comprises a layer of conductive material positioned above said at least one layer of metal. 
     
     
         19 . The FinFET device of  claim 13 , further comprising a gate cap layer positioned above said gate structure, wherein said sidewall spacers are positioned adjacent and laterally confine said gate cap layer.