Manufacturing method of semiconductor device

Abstract

To provide a manufacturing method of a semiconductor device including a memory cell having a higher reliability. First and second stacked structures in a memory cell formation region are formed so as to have a larger height than a third stacked structure in a transistor formation region, and then an interlayer insulating layer is formed so as to cover these stacked structures and then polished.

What is claimed is: 
     
         1 . A method of manufacturing a semiconductor device including a memory cell of a nonvolatile memory formed in a first region of a semiconductor substrate and a MOS-type transistor formed in a second region of the semiconductor substrate, the method including:
 (a) forming a first dummy gate electrode over the semiconductor substrate via a first insulating film and a second dummy gate electrode over the semiconductor substrate via a second insulating film in the first region, and forming a third dummy gate electrode over the semiconductor substrate via a third insulating film in the second direction, the second dummy gate electrode being disposed adjacent to the first dummy gate electrode via a fourth insulating film, the second dummy gate electrode having a height from a surface of the semiconductor substrate to an upper surface of the second dummy gate electrode that is greater than a height of the third dummy gate electrode from the surface of the semiconductor substrate to an upper surface of the third dummy gate electrode;   (b) forming an interlayer insulating layer so as to overlap an upper surface of the first dummy gate electrode, the upper surface of the second dummy gate electrode and the upper surface of the third dummy gate electrode;   (c) polishing parts of the interlayer insulating layer, the first dummy gate electrode, the second dummy gate electrode, and the third dummy electrodes so that the upper surfaces of the first dummy gate electrode, the second dummy gate electrode and third dummy electrode are exposed from the interlayer insulating layer;   (d) after step (c), removing the first dummy electrode, the second dummy electrode and the third dummy electrode; and   (e) after step (d), filling a metal-containing film in a first opening part which is a region from which the first dummy gate electrode has been removed in step (d), a second opening part which is a region from which the second dummy gate electrode has been removed in step (d) and a third opening part which is a region from which the third dummy gate electrode has been removed in step (d).