Semiconductor devices with replacement gate structures

Abstract

A transistor device includes a semiconductor substrate and a gate structure positioned above a surface of the semiconductor substrate. The gate structure includes a high-k gate insulation layer positioned above the surface of the semiconductor substrate and at least one work-function adjusting layer of material positioned above the high-k gate insulation layer, wherein an upper surface of the at least one work-function adjusting layer of material has a stepped profile when viewed in cross-section taken in a gate-width direction of the transistor device. The gate structure further includes a layer of conductive material positioned on the stepped upper surface of the at least one work-function adjusting layer of material.

What is claimed: 
     
         1 . A transistor device, comprising:
 a semiconductor substrate; and   a gate structure positioned above a surface of said semiconductor substrate, said gate structure comprising:
 a high-k gate insulation layer positioned above said surface of said semiconductor substrate; 
 at least one work-function adjusting layer of material positioned above said high-k gate insulation layer, wherein an upper surface of said at least one work-function adjusting layer of material has a stepped profile when viewed in cross-section taken in a gate-width direction of said transistor device; and 
 a layer of conductive material positioned on said stepped upper surface of said at least one work-function adjusting layer of material. 
   
     
     
         2 . The device of  claim 1 , wherein said stepped profile of said upper surface of said at least one work-function adjusting layer of material comprises a plurality of substantially planar surfaces that are spaced apart from one another in said gate-width direction. 
     
     
         3 . The device of  claim 2 , wherein an upper surface of each of said plurality of substantially planar spaced-apart surfaces is positioned at approximately a same height level above said surface of said semiconductor substrate. 
     
     
         4 . The device of  claim 2 , wherein said stepped profile of said upper surface of said at least one work-function adjusting layer of material further comprises at least one projection positioned between said plurality of spaced-apart, substantially planar surfaces, an upper surface of said at least one projection being positioned at a height level above said upper surface of said semiconductor substrate that is greater than a height level of an upper surface of said spaced-apart, substantially planar surfaces above said upper surface of said semiconductor substrate. 
     
     
         5 . The device of  claim 4 , wherein said at least one projection comprises an opening extending below said upper surface of said at least one projection. 
     
     
         6 . The device of  claim 5 , wherein said layer of conductive material fills said opening extending below said upper surface of said at least one projection. 
     
     
         7 . The device of  claim 2 , wherein said stepped profile of said upper surface of said at least one work-function adjusting layer of material further comprises at least one recess positioned between said plurality of spaced-apart, substantially planar surfaces, an upper surface of said at least one recess being positioned at a height level above said upper surface of said semiconductor substrate that is less than a height level of an upper surface of said spaced-apart, substantially planar surfaces above said upper surface of said semiconductor substrate. 
     
     
         8 . The device of  claim 1 , wherein said stepped profile of said upper surface of said at least one work-function adjusting layer of material comprises a plurality of periodically spaced-apart upper surface portions, each of said plurality of periodically spaced-apart upper surface portions having a substantially planar upper surface that is positioned at approximately a same height level above said upper surface of said semiconductor substrate. 
     
     
         9 . The device of  claim 1 , further comprising a sidewall spacer positioned adjacent opposite sides of said gate structure. 
     
     
         10 . The device of  claim 9 , further comprising a gate cap layer positioned above said layer of conductive material. 
     
     
         11 . The device of  claim 10 , wherein said sidewall spacer is positioned adjacent opposite sides of said gate cap layer. 
     
     
         12 . A transistor device, comprising:
 a semiconductor substrate;   a gate structure positioned above a surface of said semiconductor substrate, said gate structure comprising:
 a high-k gate insulation layer positioned above said surface of said semiconductor substrate; 
 at least one work-function adjusting layer of material positioned above said high-k gate insulation layer, wherein an upper surface of said at least one work-function adjusting layer of material has a stepped profile when viewed in cross-section taken in a gate-width direction of said transistor device, said stepped profile comprising a plurality of substantially planar surfaces that are spaced apart from one another in said gate-width direction, wherein an upper surface of each of said plurality of substantially planar spaced-apart surfaces is positioned at approximately a same height level above said surface of said semiconductor substrate; and 
 a layer of conductive material positioned on said stepped upper surface of said at least one work-function adjusting layer of material; 
   a gate cap layer positioned above said layer of conductive material; and   a sidewall spacer positioned adjacent opposite sides of each of said gate structure and said gate cap layer.   
     
     
         13 . The device of  claim 12 , wherein said stepped profile of said upper surface of said at least one work-function adjusting layer of material further comprises at least one projection positioned between said plurality of spaced-apart, substantially planar surfaces, an upper surface of said at least one projection being positioned at a height level above said upper surface of said semiconductor substrate that is greater than a height level of an upper surface of said spaced-apart, substantially planar surfaces above said upper surface of said semiconductor substrate. 
     
     
         14 . The device of  claim 12 , wherein said stepped profile of said upper surface of said at least one work-function adjusting layer of material further comprises at least one recess positioned between said plurality of spaced-apart, substantially planar surfaces, an upper surface of said at least one recess being positioned at a height level above said upper surface of said semiconductor substrate that is less than a height level of an upper surface of said spaced-apart, substantially planar surfaces above said upper surface of said semiconductor substrate. 
     
     
         15 . The device of  claim 12 , wherein said stepped profile of said upper surface of said at least one work-function adjusting layer of material comprises a plurality of periodically spaced-apart upper surface portions, each of said plurality of periodically spaced-apart upper surface portions having a substantially planar upper surface that is positioned at approximately a same height level above said upper surface of said semiconductor substrate. 
     
     
         16 . A transistor device, comprising:
 a semiconductor substrate;   a gate structure positioned above a surface of said semiconductor substrate, said gate structure comprising:
 a gate insulation layer positioned above said surface of said semiconductor substrate; 
 a layer of gate electrode material positioned above said gate insulation layer, wherein an upper surface of said layer of gate electrode material has a stepped profile when viewed in cross-section taken in a gate-width direction of said transistor device, said stepped profile comprising:
 a plurality of periodically spaced-apart upper surface portions, each of said plurality of periodically spaced-apart upper surface portions having a substantially planar upper surface that is positioned at approximately a same first height level above said upper surface of said semiconductor substrate; 
 a projection positioned between a first two of said plurality of spaced-apart upper surface portions, wherein an upper surface of said projection is positioned at a second height level above said upper surface of said semiconductor substrate that is greater than said first height level; and 
 a recess positioned between a second two of said plurality of spaced-apart upper surface portions, wherein an upper surface of said recess is positioned at a third height level above said upper surface of said semiconductor substrate that is less than said first height level; and 
 
 a layer of conductive material positioned on said stepped upper surface of said layer of gate electrode material; and 
   a sidewall spacer positioned adjacent opposite sides of at least a portion of said gate structure.   
     
     
         17 . The device of  claim 16 , further comprising a gate cap layer positioned above said layer of conductive material, wherein said sidewall spacer is positioned adjacent opposite sides of at least a portion of said gate gap layer. 
     
     
         18 . The device of  claim 16 , wherein said gate insulation layer comprises a high-k dielectric material having a dielectric constant of approximately 10 or greater. 
     
     
         19 . The device of  claim 16 , wherein said layer of gate electrode material comprises at least one work-function adjusting metal layer. 
     
     
         20 . The device of  claim 16 , wherein said gate structure is an HK/MG replacement gate structure.