US2016093710A1PendingUtilityA1
Semiconductor device and method for forming the same
Est. expiryJan 2, 2034(~7.4 yrs left)· nominal 20-yr term from priority
Inventors:Young Doo Jeong
H10B 12/053H10D 64/668H10D 64/663H10D 64/518H10D 64/035H10D 64/513H10D 64/517H10D 64/512H10D 64/62H10D 30/477H10D 30/0212H10D 30/025H01L 29/4933H01L 29/401H01L 29/665H01L 29/4236H01L 27/10876
35
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Claims
Abstract
A semiconductor device includes a junction region on both sides of a trench in a semiconductor substrate, a first gate electrode with a first workfunction buried in the trench, and a second gate electrode formed of a polycide layer having a second workfunction overlapping with the junction region at an upper part of the first gate electrode.
Claims
exact text as granted — not AI-modified1 - 11 . (canceled)
12 . A method for forming a semiconductor device comprising:
forming a trench by etching a gate region of a semiconductor substrate; forming a first gate electrode having a first workfunction in the trench; forming spaces between an upper portion of the first gate electrode and sidewalls of the trench; and forming a second gate electrode over the first gate electrode in such a manner that the second gate electrode overlaps with a junction region of the semiconductor substrate and is formed of a polycide material having a second workfunction.
13 . The method according to claim 12 , wherein forming the spaces includes:
forming a barrier metal layer over sidewalls of the trench; and etching a portion of the barrier metal layer disposed between sidewalls of the upper portion of the first gate electrode and sidewalls of the trench.
14 . The method according to claim 12 , wherein forming the second gate electrode includes:
depositing a polysilicon layer over a top surface of the first gate electrode and in the spaces between the upper portion of the first gate electrode and sidewalls of the trench; implanting impurities in the polysilicon layer; and performing a silicidation process on the polysilicon layer.
15 . The method according to claim 14 , wherein the silicidation process includes forming a silicide in the first gate electrode.
16 . The method according to claim 12 , further comprising:
before forming the first gate electrode, forming a gate insulation film over sidewalls of the trench.
17 . The method according to claim 16 , further comprising forming a barrier metal film over the first gate electrode
18 . The method according to claim 17 , wherein forming the spaces between the upper portion of the first gate electrode and sidewalls of the trench includes etching upper portions of the barrier metal film, wherein side portions of the second gate electrode are formed in the spaces.
19 . The method according to claim 12 , wherein the second workfunction is substantially the same as a workfunction of polysilicon.
20 . The method according to claim 14 , wherein the impurity is an N-type.Join the waitlist — get patent alerts
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