Transistor-Containing Constructions and Memory Arrays

Abstract

Some embodiments include transistor-containing constructions having gate material within an opening in a semiconductor material and spaced from the semiconductor material by gate dielectric material. The opening has a wide lower region beneath a narrow upper region. A saddle region of the gate dielectric material extends outwardly from a bottom of the opening and is along the semiconductor material beneath the opening. A saddle region of the gate material extends outwardly from the bottom of the opening and is along the gate dielectric material beneath the opening. Source/drain regions are within the semiconductor material along sides of the gate material. Some embodiments include memory arrays.

1 - 35 . (canceled) 
     
     
         36 . A transistor-containing construction, comprising:
 a recess extending into a semiconductor material; the recess having a narrow upper region and a wide lower region;   gate material within a bottom portion of the wide lower region; the gate material extending outwardly from the bottom of the recess and downwardly to beneath the recess; and   a pair of spaced-apart source/drain regions within the semiconductor material along sides of the recess, with a channel region being between the spaced-apart source/drain regions.   
     
     
         37 . The construction of  claim 36  wherein the gate material is within both the narrow upper region of the recess and the wide lower region of the recess. 
     
     
         38 . The construction of  claim 36  wherein insulative material is over the gate material within the recess and directly contacts the gate material along an interface; the insulative material being within a top portion of the wide lower region, and being within the narrow upper region; the source/drain regions vertically overlapping the interface of the insulative material and the gate material. 
     
     
         39 . The construction of  claim 38  wherein the gate material within the recess is comprised by a wordline extending through the recess; wherein the gate material extending outwardly from the bottom of the recess forms a saddle region along the semiconductor material; and wherein said saddle region has a width about the same as a width of the wordline. 
     
     
         40 . The construction of  claim 38  wherein the gate material within the recess is comprised by a wordline extending through the recess; wherein the gate material extending outwardly from the bottom of the recess forms a saddle region along the semiconductor material; and wherein said saddle region has a width less than a width of the wordline. 
     
     
         41 . The construction of  claim 38  wherein the recess substantially has mirror symmetry along a plane extending vertically along a center of the recess. 
     
     
         42 . The construction of  claim 38  wherein the recess does not have mirror symmetry along a plane extending vertically along a center of the recess. 
     
     
         43 . The construction of  claim 38  wherein the narrow upper region is inset relative to the wide lower region by a step along one side of the recess. 
     
     
         44 . The construction of  claim 43  wherein the step is a first step, and further comprising a second step on an opposing side of the narrow upper region from the first step. 
     
     
         45 . A transistor-containing construction, comprising:
 gate material within an opening in a silicon-containing material, and spaced from the silicon-containing material by gate dielectric material;   insulative material over the gate material and directly contacting the gate material along an interface, the insulative material being within the opening; the insulative material having a narrow section over a wide section; the wide section having a same width as the gate material; the insulative material comprising one or both of silicon dioxide and silicon nitride;   a saddle region of the gate dielectric material extending outwardly from a bottom of the opening and along the silicon-containing material beneath the opening;   a saddle region of the gate material extending outwardly from the bottom of the opening and along the gate dielectric material beneath the opening; and   source/drain regions within the silicon-containing material along sides of the insulative material and gate material, the source/drain regions vertically overlapping the interface of the insulative material and the gate material.   
     
     
         46 . The construction of  claim 45  wherein the gate material within the opening has a first width; and wherein the saddle region gate material has a second width which is about the same as the first width. 
     
     
         47 . The construction of  claim 45  wherein the gate material within the opening has a first width; and wherein the saddle region gate material has a second width which is less than the first width. 
     
     
         48 . The construction of  claim 45  wherein the insulative material and the gate material substantially have mirror symmetry along a plane extending vertically along a center through the insulative material and the gate material. 
     
     
         49 . The construction of  claim 45  wherein the insulative material and the gate material do not have mirror symmetry along a plane extending vertically along a center through the insulative material and the gate material. 
     
     
         50 . A memory array, comprising:
 a plurality of transistor constructions within a semiconductor material; each transistor construction comprising:
 gate material within an opening in the semiconductor material, and spaced from the semiconductor material by gate dielectric material; the gate material within the opening being part of a wordline; 
 a saddle region of the gate dielectric material extending outwardly from a bottom of the opening and along the semiconductor material beneath the opening; 
 a saddle region of the gate material extending outwardly from the bottom of the opening and along the gate dielectric material beneath the opening; and 
 source/drain regions within the semiconductor material along sides of the gate material; and 
   a pair of adjacent transistor constructions sharing a source/drain region; the shared source/drain region being connected to a bitline; the adjacent transistor constructions also comprising source/drain regions which are not shared, and which are connected to memory structures.   
     
     
         51 . The memory array of  claim 50  wherein the memory structures are capacitors. 
     
     
         52 . The memory array of  claim 50  wherein an individual transistor construction has gate material within the opening having a first width; and has saddle region gate material having a second width which is about the same as the first width. 
     
     
         53 . The memory array of  claim 50  wherein an individual transistor construction has gate material within the opening having a first width; and has saddle region gate material having a second width which is less than the first width.