Double gated flash memory

Abstract

A split gate memory cell is fabricated with a fin structure between a memory gate stack and a select gate. Embodiments include a first channel region under the memory gate stack and a second channel region under the select gate.

What is claimed is: 
     
         1 . A device comprising:
 a fin structure on a substrate;   a memory gate stack proximate a first side surface of the fin structure; and   a select gate proximate a second side surface of the fin structure.   
     
     
         2 . The device according to  claim 1 , comprising:
 a first channel region under the memory gate stack; and   a second channel region under the select gate.   
     
     
         3 . The device according to  claim 2 , wherein the first channel region is for program and/or erase and the second channel region is for read. 
     
     
         4 . The device according to  claim 1 , comprising the memory gate stack and the select gate being on opposite side surfaces of the fin structure. 
     
     
         5 . The device according to  claim 4 , wherein the memory gate stack comprises:
 a floating gate proximate the fin structure; and   a control gate proximate the floating gate.   
     
     
         6 . The device according to  claim 5 , further comprising an oxide between the select gate and the fin structure and between the floating gate and the fin structure. 
     
     
         7 . The device according to  claim 6 , further comprising a dielectric layer between the floating gate and the control gate. 
     
     
         8 . The device according to  claim 1 , further comprising:
 a second fin structure proximate the select gate.   
     
     
         9 . The device according to  claim 8 , further comprising:
 a second memory gate stack proximate a side surface of the second fin structure, opposite the select gate.   
     
     
         10 . The device according to  claim 1 , further comprising:
 a second memory gate stack on the substrate proximate, but separated from the select gate.   
     
     
         11 . The device according to  claim 10 , further comprising:
 a second fin structure proximate the second memory gate stack; and   a second select gate proximate the second fin structure, opposite the second memory gate stack.   
     
     
         12 . A device comprising:
 a fin structure on a substrate;   a memory gate stack proximate a first side surface of the fin structure; and   a select gate proximate a second side surface of the fin structure,   wherein the memory gate stack and select gate are substantially coplanar with the upper surface of the fin structure, and   the memory gate stack includes a floating gate proximate the fin structure, and a control gate proximate the floating gate.   
     
     
         13 . The device according to  claim 12 , comprising:
 a first channel region under the memory gate stack; and   a second channel region under the select gate.   
     
     
         14 . The device according to  claim 13 , wherein the first channel region is for program and/or erase and the second channel region is for read. 
     
     
         15 . The device according to  claim 12 , comprising the memory gate stack and the select gate being on opposite side surfaces of the fin structure. 
     
     
         16 . The device according to  claim 12 , further comprising an oxide between the select gate and the fin structure and between the floating gate and the fin structure. 
     
     
         17 . The device according to  claim 12 , further comprising a dielectric layer between the floating gate and the control gate. 
     
     
         18 . The device according to  claim 12 , further comprising:
 a second fin structure proximate the select gate.   
     
     
         19 . The device according to  claim 18 , further comprising:
 a second memory gate stack proximate a side surface of the second fin structure, opposite the select gate.   
     
     
         20 . A device comprising:
 a substrate comprising a first fin structure and a second fin structure, separated from the first fin structure;   a select gate between the first and second fin structures, proximate a first side surface of each of the first and second fin structures;   a floating gate proximate a second side surface of each of the first and second fin structures;   a first dielectric layer proximate a side surface of the floating gate material proximate the first fin structure and a second dielectric layer proximate a side surface of the floating gate material proximate the second fin structure; and   a control gate proximate the first and second dielectric layers,   wherein the select gate material, floating gate material, and first and second fin structures are substantially coplanar.