Semiconductor device

Abstract

A semiconductor device includes a first semiconductor chip and a second semiconductor chip, and wherein the first semiconductor chip includes a plurality of first bonding pads, and the second semiconductor chip includes a plurality of second bonding pads for coupling respectively to the first bonding pads by wire-bonding coupling and at least one third bonding pad for enabling relay coupling of a corresponding second bonding pad to at least one predetermined first bonding pad which is arranged along the second bonding pads and included in the first bonding pads without crossing another wire in the wire-bonding coupling.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a first semiconductor chip and a second semiconductor chip, and   wherein the first semiconductor chip includes a plurality of first bonding pads, and   the second semiconductor chip includes   a plurality of second bonding pads for coupling respectively to the first bonding pads by wire-bonding coupling and   at least one third bonding pad for enabling relay coupling of a corresponding second bonding pad to at least one predetermined first bonding pad which is arranged along the second bonding pads and included in the first bonding pads without crossing another wire in the wire-bonding coupling.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein each of the first bonding pads includes a signal pad. 
     
     
         3 . The semiconductor device according to  claim 1 , further comprising:
 a package substrate over which the first semiconductor chip and the second semiconductor chip are mounted,   wherein the first semiconductor chip includes the first bonding pads arranged along one side of the first semiconductor chip,   the package substrate is arranged along one side of the substrate, and includes second bonding pads to be coupled to the first bonding pads by wire-bonding coupling, and   the second semiconductor chip includes at least one third bonding pad for enabling relay coupling of a corresponding second bonding pad by wire-bonding coupling to at least one predetermined first bonding pad arranged along the second bonding pads and included in the first bonding pads without crossing another wire in the wire-bonding coupling.   
     
     
         4 . The semiconductor device according to  claim 2 ,
 wherein each of the first bonding pads includes a power source pad.   
     
     
         5 . The semiconductor device according to  claim 1 ,
 wherein the at least one third bonding pad is arranged between the first bonding pads and the second bonding pads.   
     
     
         6 . The semiconductor device according to  claim 1 ,
 wherein the third bonding pad includes a plurality of third bonding pads, and   the plurality of third bonding pads are arranged parallelly along the second bonding pads.   
     
     
         7 . The semiconductor device according to  claim 1 ,
 wherein the third bonding pad includes a plurality of third bonding pads, and   the plurality of third bonding pads are arranged in series along the second bonding pads.   
     
     
         8 . The semiconductor device according to  claim 1 ,
 wherein the first semiconductor chip includes a memory chip having a storage cell storing data.   
     
     
         9 . The semiconductor device according to  claim 1 ,
 wherein the second semiconductor chip includes a logical chip having a logic circuit.   
     
     
         10 . The semiconductor device according to  claim 1 , wherein the first bonding pads, the second bonding pads, and the at least one third bonding pad are formed in a same metallization layer. 
     
     
         11 . A semiconductor device, comprising:
 a first semiconductor chip and a second semiconductor chip, and wherein the first semiconductor chip includes a plurality of first pads, and   the second semiconductor chip includes   a plurality of second pads for coupling respectively to the first pads by wire coupling and   at least one third pad for enabling relay coupling of a corresponding second pad to at least one predetermined first pad which is arranged along the second pads and included in the first pads without crossing another wire in the wire coupling.   
     
     
         12 . The semiconductor device according to  claim 11 ,
 wherein each of the first pads includes a signal pad.   
     
     
         13 . The semiconductor device according to  claim 11 , further comprising:
 a package substrate over which the first semiconductor chip and the second semiconductor chip are mounted, and   wherein the first semiconductor chip includes the first pads arranged along one side of the first semiconductor chip,   the package substrate includes along one side thereof second pads to be coupled to the first pads by wire coupling, and   the second semiconductor chip includes at least one third pad for enabling relay coupling of a corresponding second pad by wire coupling to at least one predetermined first pad arranged along the second pads and included in the first pads without crossing another wire in the wire coupling.   
     
     
         14 . The semiconductor device according to  claim 12 ,
 wherein each of the first pads includes a power source pad.   
     
     
         15 . The semiconductor device according to  claim 11 ,
 wherein the at least one third pad is arranged between the first pads and the second pads.   
     
     
         16 . The semiconductor device according to  claim 11 ,
 wherein the at least one third pad includes a plurality of third pads, and   the plurality of third pads are arranged parallelly along the second pads.   
     
     
         17 . The semiconductor device according to  claim 11 ,
 wherein the at least one third pad includes a plurality of third pads, and   the plurality of third pads are arranged in series along the second pads.   
     
     
         18 . The semiconductor device according to  claim 11 ,
 wherein the first semiconductor chip includes a memory chip having a storage cell storing data, and   wherein the second semiconductor chip includes a logical chip having a logic circuit.   
     
     
         19 . The semiconductor device according to  claim 11 , wherein the first pads, the second pads, and the at least one third pad are formed in a same metallization layer. 
     
     
         20 . A method of forming a semiconductor device, said method comprising:
 mounting a first semiconductor chip and a second semiconductor chip over a package substrate, wherein the first semiconductor chip includes a plurality of first bonding pads;   arranging the first bonding pads along one side of the first semiconductor chip, wherein the second semiconductor chip includes a plurality of second bonding pads;   arranging the plurality of second bonding pads along one side of the second semiconductor chip;   coupling the plurality of second bonding pads respectively to the first bonding pads by wire-bonding coupling; and   enabling, by at least one third bonding pad, relay coupling of a corresponding second bonding pad to at least one predetermined first bonding pad which is arranged along the second bonding pads and included in the first bonding pads without crossing another wire in the wire-bonding coupling.