US2016093583A1PendingUtilityA1

Bond pad with micro-protrusions for direct metallic bonding

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Assignee: MICRON TECHNOLOGY INCPriority: Sep 25, 2014Filed: Sep 25, 2014Published: Mar 31, 2016
Est. expirySep 25, 2034(~8.2 yrs left)· nominal 20-yr term from priority
Inventors:Aibin YuWei ZhouZhaohui Ma
H10W 20/0245H10W 72/952H10W 72/9415H10W 72/932H10W 72/924H10W 72/923H10W 72/01953H10W 72/01935H10W 80/312H10W 72/941H10W 80/334H10W 90/792H10W 90/297H10W 90/00H10W 80/011H10W 72/07252H10W 72/934H10W 72/228H10W 72/90H10W 72/072H10W 20/023H10W 20/20H10W 99/00H10W 72/20H01L 23/481H01L 24/14H01L 24/09H01L 2224/1701H01L 2924/01029H01L 24/81
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Claims

Abstract

A bond pad with micro-protrusions for direct metallic bonding. In one embodiment, a semiconductor device comprises a semiconductor substrate, a through-silicon via (TSV) extending through the semiconductor substrate, and a copper pad electrically connected to the TSV and having a coupling side. The semiconductor device further includes a copper element that projects away from the coupling side of the copper pad. In another embodiment, a bonded semiconductor assembly comprises a first semiconductor substrate with a first TSV and a first copper pad electrically coupled to the first TSV, wherein the first copper pad has a first coupling side. The bonded semiconductor assembly further comprises a second semiconductor substrate, opposite to the first semiconductor substrate, the second semiconductor substrate comprising a second copper pad having a second coupling side. A plurality of copper connecting elements extend between the first and second coupling sides of the first and second copper pads.

Claims

exact text as granted — not AI-modified
1 . A semiconductor device comprising:
 a semiconductor substrate;   a through-silicon via (TSV) extending through the semiconductor substrate;   a copper pad electrically connected to the TSV and having a coupling side;   a dielectric material disposed over the coupling side of the copper pad; and   a plurality of metallic elements that project away from the coupling side of the copper pad, the metallic elements separated from each other across the copper pad, wherein the dielectric material is disposed between adjacent metallic elements.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the TSV comprises copper. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the plurality of metallic elements comprise copper pillars. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the plurality of metallic elements comprises at least four metallic elements. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the plurality of metallic elements project beyond the dielectric material. 
     
     
         6 . The semiconductor device of  claim 5 , wherein the plurality of metallic elements project beyond the dielectric material by between 0.5 and 2 microns. 
     
     
         7 . The semiconductor device of  claim 1 , wherein each of the plurality of metallic elements has a cross-sectional dimension of between 0.5 and 5 microns. 
     
     
         8 . The semiconductor device of  claim 1 , wherein the plurality of metallic elements are configured to deform under pressure of less than or equal to 20 MPa. 
     
     
         9 . A semiconductor device comprising:
 a substrate comprising an interconnect extending therethrough;   a dielectric material on the substrate;   a metallic bond pad embedded in the dielectric material and electrically coupled to an end portion of the interconnect;   a plurality of metallic bonding elements electrically coupled to the metallic bond pad and projecting from the bond pad, the metallic bonding elements separated from each other across the metallic bond pad and extending through the dielectric material, the metallic bonding elements having a lower portion embedded in the dielectric material, and the metallic bonding elements configured to deform under less pressure than the metallic bond pad.   
     
     
         10 . The semiconductor device of  claim 9 , wherein the metallic bond pad comprises copper, and wherein the plurality of metallic bonding elements comprise copper. 
     
     
         11 . The semiconductor device of  claim 9 , wherein the metallic bonding elements have an upper portion that projects beyond the dielectric material. 
     
     
         12 . The semiconductor device of  claim 9 , wherein the plurality of metallic bonding elements comprise at least four metallic bonding elements. 
     
     
         13 . The semiconductor device of  claim 9 , wherein the plurality of metallic bonding elements comprise pillars. 
     
     
         14 . The semiconductor device of  claim 9 , wherein the plurality of metallic bonding elements project beyond the dielectric material by between 0.5 and 2 microns. 
     
     
         15 . The semiconductor device of  claim 9 , wherein the plurality of metallic bonding elements each has a cross-sectional dimension of between 0.5 and 5 microns. 
     
     
         16 . A bonded semiconductor assembly comprising:
 a first semiconductor substrate comprising a first through-silicon via (TSV) and a first copper pad electrically coupled to the first TSV, wherein the first copper pad has a first coupling side;   a second semiconductor substrate opposite to the first substrate, the second semiconductor substrate comprising a second copper pad having a second coupling side; and   a plurality of copper connecting elements extending between the first and second coupling sides of the first and second copper pads.   
     
     
         17 . The bonded semiconductor assembly of  claim 16 , wherein the first and second TSVs each comprises copper. 
     
     
         18 . The bonded semiconductor assembly of  claim 16 , wherein the plurality of copper connecting elements comprise pillars. 
     
     
         19 . The bonded semiconductor assembly of  claim 16 , wherein the plurality of copper connecting elements comprise at least four copper connecting elements. 
     
     
         20 . The bonded semiconductor assembly of  claim 16 , further comprising a dielectric material at least partially surrounding the plurality of copper connecting elements. 
     
     
         21 . The bonded semiconductor assembly of  claim 16 , wherein the plurality of copper connecting elements each has a cross-sectional dimension of between 0.5 and 5 microns. 
     
     
         22 . The bonded semiconductor assembly of  claim 16 , wherein the plurality of copper connecting elements are in electrical communication with both the first and second copper pads. 
     
     
         23 . A semiconductor device, comprising:
 a first semiconductor substrate having a first through-silicon via (TSV), a first pad electrically coupled to the first TSV, and a first bonding feature projecting away from the first pad, wherein the first bonding feature covers only a portion of the first pad; and   a second semiconductor substrate having a second TSV, a second pad electrically coupled to the second TSV, and a second bonding feature projecting away from the second pad, wherein the second bonding feature covers only a portion of the second pad;   wherein the first bonding feature is directly connected to the second bonding feature by a metal-to-metal bond.   
     
     
         24 . The semiconductor device of  claim 23 , wherein the first and second pads each comprise copper, and wherein the first and second bonding features each comprise copper. 
     
     
         25 . The semiconductor device of  claim 23 , wherein the first bonding feature comprises a pillar. 
     
     
         26 . The semiconductor device of  claim 23 , further comprising a dielectric material disposed between the first pad and the second pad, the dielectric material at least partially surrounding the first bonding feature. 
     
     
         27 . The semiconductor device of  claim 23 , wherein the first and second bonding features each comprise metallic elements. 
     
     
         28 . A semiconductor device, comprising:
 a first semiconductor substrate having a first through-silicon via (TSV), a first pad electrically coupled to the first TSV, and a first bonding feature projecting away from the first pad, wherein the first bonding feature covers only a portion of the first pad; and   a second semiconductor substrate having a second TSV and a second pad electrically coupled to the second TSV;   wherein the first bonding feature is directly connected to the second pad by a metal-to-metal bond.   
     
     
         29 . The semiconductor device of  claim 28 , further comprising a dielectric material disposed between the first pad and the second pad, the dielectric material at least partially surrounding the first bonding feature. 
     
     
         30 . The semiconductor device of  claim 28 , wherein the first and second pads each comprises copper, and wherein the first bonding feature comprises copper. 
     
     
         31 . The semiconductor device of  claim 28 , wherein the first bonding feature each has a cross-sectional dimension of between 0.5 and 5 microns. 
     
     
         32 . A method of manufacturing a semiconductor device, the method comprising:
 forming dielectric material over a bond pad electrically coupled to an interconnect that extends through a substrate;   forming openings in the dielectric material over the bond pad; and   forming a conductive material in the openings, the conductive material electrically coupled to the bond pad and projecting away from the bond pad to define a metallic bonding element.   
     
     
         33 . The method of  claim 32 , wherein the conductive material comprises copper. 
     
     
         34 . The method of  claim 32 , further comprising planarizing the conductive material to form separate conductive elements projecting away from the bond pad. 
     
     
         35 . The method of  claim 34 , further comprising etching a portion of the dielectric material such that the separate conductive elements project beyond the dielectric material. 
     
     
         36 . The method of  claim 32 , further comprising bonding the semiconductor device to a second semiconductor device having a second bond pad. 
     
     
         37 . The method of  claim 36 , wherein the conductive material is in electrical communication with the first bond pad and the second bond pad. 
     
     
         38 . The method of  claim 32 , further comprising bonding the metallic bonding element to a second metallic bonding element projecting from a bond pad of a second semiconductor device. 
     
     
         39 . A method of manufacturing a semiconductor device, the method comprising:
 providing a first semiconductor substrate having a first through-silicon via (TSV), a first pad electrically coupled to the first TSV, and a first bonding feature projecting away from the first pad;   disposing a second semiconductor substrate, having a second TSV and a second pad electrically coupled to the second TSV, over the first semiconductor substrate such that the first pad faces the second pad; and   bonding the first semiconductor substrate to the second semiconductor substrate such that the first bonding feature is electrically coupled to the second pad.   
     
     
         40 . The method of  claim 39 , wherein bonding the first semiconductor substrate to the second semiconductor substrate comprises applying pressure of less than or equal to 20 MPa. 
     
     
         41 . The method of  claim 39 , wherein bonding the first semiconductor substrate to the second semiconductor substrate comprises directly connecting the first bonding feature to the second pad. 
     
     
         42 . The method of  claim 41 , wherein the first and second pads each comprises copper, and wherein the first bonding feature comprises copper. 
     
     
         43 . The method of  claim 41 , wherein the first bonding feature comprises a pillar. 
     
     
         44 . The method of  claim 41 , wherein bonding the first semiconductor substrate to the second semiconductor substrate comprises at least partially deforming the first bonding feature. 
     
     
         45 . The method of  claim 39 , wherein the second semiconductor substrate further comprises a second bonding feature projecting away from the second pad, and wherein bonding the first semiconductor substrate to the semiconductor substrate comprises directly connecting the first bonding feature to the second bonding feature. 
     
     
         46 . The method of  claim 45 , wherein during bonding the first bonding feature is substantially aligned with the second bonding feature. 
     
     
         47 . The method of  claim 45 , wherein during bonding the first bonding feature is at least partially offset with respect to the second bonding feature. 
     
     
         48 . The method of  claim 45 , wherein bonding the first semiconductor substrate to the second semiconductor substrate comprises at least partially deforming the first and second bonding features. 
     
     
         49 . The method of  claim 45 , wherein the first and second pads each comprises copper, and wherein the first and second bonding features each comprises copper. 
     
     
         50 . The method of  claim 45 , wherein the first and second bonding features each comprises a pillar.

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