US2016092625A1PendingUtilityA1

Integrated circuit inductors

Assignee: NXP BVPriority: Dec 6, 2010Filed: Oct 26, 2015Published: Mar 31, 2016
Est. expiryDec 6, 2030(~4.4 yrs left)· nominal 20-yr term from priority
H01F 41/041H01F 17/0013H01F 27/2804H01F 2017/0073H01F 17/0006Y10T29/49004H01F 27/34H01F 5/003G06F 30/392G06F 17/5072
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Claims

Abstract

An integrated circuit inductor design is provided in which the path crossings are designed such that the voltage differences between the adjacent paths in the loops are (in total) minimised.

Claims

exact text as granted — not AI-modified
1 - 12 . (canceled) 
     
     
         13 . A method of designing the layout of an inductor comprising a conducting track arranged in loops, each loop comprising at least two concentric paths, wherein the track length comprises tap regions at the ends of the tracks and a central track region which comprises the concentric paths of the loops, wherein the central track region comprises a sequence of track sections, each comprising a loop half turn, and crossings between tracks sections, with the crossings spaced along the central track region by one or two track sections,
 wherein the method comprises defining a parameter p:   p=the sum of squares of normalised differences in track section sequence number for all adjacent pairs of track sections in each loop; and   
       selecting the path crossings at locations such that the parameter p is the minimum possible value of p.

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