Systems, Apparatuses, and Methods for Zeroing of Bits in a Data Element

Abstract

Embodiments of systems, methods and apparatuses for execution a NAME instruction are described. The execution of a VPBZHI causes, on a per data element basis of a second source, a zeroing of bits higher (more significant) than a starting point in the data element. The starting point is defined by the contents of a data element in a first source. The resultant data elements are stored in a corresponding data element position of a destination.

What is claimed is: 
     
         1 . An apparatus comprising:
 decode circuitry to decode an instruction, the instruction including a first and second source operand and a destination operand;   execution circuitry to execute the decoded instruction to
 determine of a starting bit position for zeroing out values of the second source operand based on the first source, 
 zero bits of the second source operand that are in bit positions that are more significant or equal to the starting bit position, and 
 store into the destination operand values of the second source operand after zeroing. 
   
     
     
         2 . The apparatus of  claim 1 , wherein the source and destination operands are packed data registers. 
     
     
         3 . The apparatus of  claim 2 , wherein the packed data registers of size 128-bit, 256-bit, or 512-bit. 
     
     
         4 . The apparatus of  claim 1 , wherein the instruction further includes a writemask operand. 
     
     
         5 . The apparatus of  claim 4 , wherein the storage in the destination operand is subject to the writemask operand's values. 
     
     
         6 . The apparatus of  claim 4 , wherein a number of active bits in the writemask operand is equal to a number of data elements in the source operands. 
     
     
         7 . The apparatus of  claim 1 , wherein the first source and destination operands are packed data registers and the second source operand is a memory location. 
     
     
         8 . A method of performing in a computer processor an instruction, the instruction including a first and second source operand and a destination operand, the method comprising:
 determining of a starting bit position for zeroing out values of the second source operand based on the first source,   zeroing bits of the second source operand that are in bit positions that are more significant or equal to the starting bit position, and   storing into the destination operand values of the second source operand after zeroing.   
     
     
         9 . The method of  claim 8 , wherein the source and destination operands are packed data registers. 
     
     
         10 . The method of  claim 9 , wherein the packed data registers of size 128-bit, 256-bit, or 512-bit. 
     
     
         11 . The method of  claim 8 , wherein the instruction further includes a writemask operand. 
     
     
         12 . The method of  claim 11 , wherein the storage in the destination operand is subject to the writemask operand's values. 
     
     
         13 . The method of  claim 11 , wherein a number of active bits in the writemask operand is equal to a number of data elements in the source operands. 
     
     
         14 . The method of  claim 8 , wherein the first source and destination operands are packed data registers and the second source operand is a memory location. 
     
     
         15 . A tangible machine-readable medium including code which when executed by a processor causes the processor to execute a method to perform an instruction, the instruction including a first and second source operand and a destination operand, the method comprising:
 determining of a starting bit position for zeroing out values of the second source operand based on the first source,   zeroing bits of the second source operand that are in bit positions that are more significant or equal to the starting bit position, and   storing into the destination operand values of the second source operand after zeroing.   
     
     
         16 . The method of  claim 15 , wherein the source and destination operands are packed data registers. 
     
     
         17 . The method of  claim 16 , wherein the packed data registers of size 128-bit, 256-bit, or 512-bit. 
     
     
         18 . The method of  claim 17 , wherein the instruction further includes a writemask operand. 
     
     
         19 . The method of  claim 18 , wherein the storage in the destination operand is subject to the writemask operand's values. 
     
     
         20 . The method of  claim 15 , wherein the first source and destination operands are packed data registers and the second source operand is a memory location.