Operational Time Extension

Abstract

Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time. Some embodiments provide a method of designing a reconfigurable IC that has several reconfigurable circuits, each having several configurations and operating in several reconfiguration cycles. The method identifies a signal path through the IC that does not meet a timing constraint. The signal path includes several circuits, one of which is a particular reconfigurable circuit. The method then maintains a configuration of the particular reconfigurable circuit constant over at least two contiguous reconfiguration cycles in order to reduce signal delay through the signal path and thereby satisfy the timing constraint.

We claims: 
     
         1 . A reconfigurable integrated circuit (“IC”) comprising:
 a) a plurality of reconfigurable circuits, each reconfigurable circuit having a plurality of configurations for a plurality of configuration cycles; 
 b) said reconfigurable circuits including a plurality of time-extending reconfigurable circuits, each particular time-extending reconfigurable circuit for maintaining a configuration over at least two contiguous cycles in order to allow a signal to propagate through a signal path, containing the particular time-extending circuit, within a desired amount of time. 
 
     
     
         2 . The reconfigurable IC of  claim 1 , wherein each reconfigurable circuit receives a plurality of configuration data set, wherein each configuration data set configures the reconfigurable circuit in a particular manner. 
     
     
         3 . The reconfigurable IC of  claim 2 , wherein during the two contiguous cycles, the particular time-extending reconfigurable circuit receives the same configuration data. 
     
     
         4 . The reconfigurable IC of  claim 1  further comprising:
 a state element for maintaining an input signal that a particular time-extending circuit receives in the two contiguous cycles constant. 
 
     
     
         5 . The reconfigurable IC of  claim 4 , wherein the state element is not a transition-sensitive storage element. 
     
     
         6 . The reconfigurable IC of  claim 4 , wherein the state element is a level sensitive storage element. 
     
     
         7 . The reconfigurable IC of  claim 6 , wherein the state element is a latch. 
     
     
         8 . The reconfigurable IC of  claim 1 , wherein at least one time-extending reconfigurable circuit is for maintaining its configuration for more than two configuration cycles. 
     
     
         9 . The reconfigurable IC of  claim 1 , wherein at least one time-extending reconfigurable circuit is on at least another signal path than the signal path that contains the time-extending reconfigurable circuit during the two reconfiguration cycles during which the time-extending circuit does not change configuration. 
     
     
         10 . A electronic device comprising:
 a reconfigurable integrated circuit (“IC”) comprising:
 a plurality of reconfigurable circuits, each reconfigurable circuit having a plurality of configurations for a plurality of configuration cycles; 
 said reconfigurable circuits including a plurality of time-extending reconfigurable circuits, each particular time-extending reconfigurable circuit for maintaining a configuration over at least two contiguous cycles in order to allow a signal to propagate through a signal path, containing the particular time-extending circuit, within a desired amount of time. 
   
     
     
         11 . A method of designing a reconfigurable integrated circuit (“IC”) that has a plurality of reconfigurable circuits having a plurality of configurations and operating in a plurality of reconfiguration cycles, the method:
 a) identifying a signal path through the IC that does not meet a timing constraint, said signal path having a plurality of circuits including at least a particular reconfigurable circuit; 
 b) maintaining a configuration of the particular reconfigurable circuit constant over at least two contiguous reconfiguration cycles in order to reduce signal delay through the signal path and thereby satisfy the timing constraint. 
 
     
     
         12 . The method of  claim 1 , wherein identifying the signal path comprises:
 a) identifying changes to the reconfiguration cycle that the reconfiguration circuits are assigned;   b) after one of the identified changes, identifying the signal path for failing to meet the timing constraint.   
     
     
         13 . The method of  claim 1 , wherein during the two contiguous cycles, the particular reconfigurable circuit receives the same configuration data. 
     
     
         14 . The method of  claim 1  further comprising:
 defining a state element before the particular reconfigurable circuit, said state element for maintaining an input signal that the particular reconfigurable circuit is to receive during the two contiguous cycles constant. 
 
     
     
         15 . The method of  claim 4 , wherein the state element is not a transition-sensitive storage element. 
     
     
         16 . The method of  claim 4 , wherein the state element is a level sensitive storage element. 
     
     
         17 . The method of  claim 6 , wherein the state element is a latch. 
     
     
         18 . The method of  claim 1 , said maintaining comprises maintaining the configuration of the particular reconfigurable circuit constant for more than two configuration cycles.