Method for fabricating semiconductor structures including transistor channels having different strain states, and related semiconductor structures

Abstract

Methods of fabricating a semiconductor structure include implanting ion into a second region of a strained semiconductor layer on a multi-layer substrate to amorphize a portion of crystalline semiconductor material in the second region of the strained semiconductor layer without amorphizing a first region of the strained semiconductor layer. The amorphous region is recrystallized, and elements are diffused within the semiconductor layer to enrich a concentration of the diffused elements in a portion of the second region of the strained semiconductor layer and alter a strain state therein relative to a strain state of the first region of the strained semiconductor layer. A first plurality of transistor channel structures are formed that each comprise a portion of the first region of the semiconductor layer, and a second plurality of transistor channel structures are formed that each comprise a portion of the second region of the semiconductor layer.

1 . A semiconductor structure, comprising:
 a base substrate,   a buried oxide layer over a surface of the base substrate,   a first plurality of transistor channel structures and a second plurality of transistor channel structures disposed over the buried oxide layer in a common plane on a side thereof opposite the base substrate, each transistor channel structure of the second plurality of transistor channel structures comprising a condensed strained semiconductor layer including two or more elements, each transistor channel structure of the first plurality of transistor channel structures comprising a non-condensed strained semiconductor layer;   wherein the transistor channel structures of the second plurality of transistor channel structures have a crystallographic strain differing from a crystallographic strain of the transistor channel structures of the first plurality of transistor channel structures.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein the non-condensed strained semiconductor layer of each transistor channel structure of the first plurality of transistor channel structures comprises strained silicon. 
     
     
         3 . The semiconductor structure of  claim 1 , wherein the condensed strained semiconductor layer of each transistor channel structure of the second plurality of transistor channel structures comprises Si x Ge 1-x , wherein x is from about 0.01 to about 0.50. 
     
     
         4 . The semiconductor structure of  claim 1 , wherein the transistor channel structures of the first plurality of transistor channel structures are in a state of tensile strain and the transistor channel structures of the first plurality of transistor channel structures are relaxed or in a state of compressive strain. 
     
     
         5 . The semiconductor structure of  claim 1 , wherein the transistor channel structures of the first plurality of transistor channel structures and the second plurality of transistor channel structures have an average width of about 15 nm or less. 
     
     
         6 . The semiconductor structure of  claim 1 , wherein the transistor channel structures of each of the first plurality of transistor channel structures and the second plurality of transistor channel structures comprise fin structures. 
     
     
         7 . The semiconductor structure of  claim 6 , further comprising a first plurality of n-type FinFET transistors comprising the first plurality of transistor channel structures, and a second plurality of p-type FinFET transistors comprising the second plurality of transistor channel structures. 
     
     
         8 . The semiconductor structure of  claim 3 , wherein the condensed strained semiconductor layer of each transistor channel structure of the second plurality of transistor channel structures comprises Si x Ge 1-x , wherein x is from about 0.10 to about 0.20. 
     
     
         9 . The semiconductor structure of  claim 4 , wherein the transistor channel structures of the first plurality of transistor channel structures are relaxed. 
     
     
         10 . The semiconductor structure of  claim 4 , wherein the transistor channel structures of the first plurality of transistor channel structures are in a state of compressive strain. 
     
     
         11 . The semiconductor structure of  claim 2 , wherein the condensed strained semiconductor layer of each transistor channel structure of the second plurality of transistor channel structures comprises Si x Ge 1-x , wherein x is from about 0.01 to about 0.50. 
     
     
         12 . The semiconductor structure of  claim 11 , wherein the transistor channel structures of the first plurality of transistor channel structures are in a state of tensile strain and the transistor channel structures of the first plurality of transistor channel structures are relaxed or in a state of compressive strain. 
     
     
         13 . The semiconductor structure of  claim 12 , wherein the transistor channel structures of the first plurality of transistor channel structures and the second plurality of transistor channel structures have an average width of about 15 nm or less. 
     
     
         14 . The semiconductor structure of  claim 12 , wherein the transistor channel structures of each of the first plurality of transistor channel structures and the second plurality of transistor channel structures comprise fin structures. 
     
     
         15 . The semiconductor structure of  claim 14 , further comprising a first plurality of n-type FinFET transistors comprising the first plurality of transistor channel structures, and a second plurality of p-type FinFET transistors comprising the second plurality of transistor channel structures. 
     
     
         16 . The semiconductor structure of  claim 1 , wherein the base substrate comprises silicon. 
     
     
         17 . The semiconductor structure of  claim 1 , wherein the buried oxide layer comprises silicon dioxide.