US2016086939A1PendingUtilityA1
Semiconductor device
Est. expirySep 27, 2032(~6.2 yrs left)· nominal 20-yr term from priority
H10D 64/663H10D 64/513H10D 64/111H10D 62/8503H10D 62/111H10D 84/811H10D 64/62H10D 62/106H10D 62/83H10D 30/603H10D 30/601H10D 30/475H10D 30/0221H10D 30/015H10D 8/60H10D 8/051H10D 62/151H01L 29/872H01L 27/0629H01L 29/456
47
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Claims
Abstract
A first contact, a second impurity region, and a second low-concentration impurity region form a Schottky barrier diode. The second impurity region has the same impurity concentration as those of first impurity regions, and thus can be formed in the same process as forming the first impurity regions. In addition, the second low-concentration impurity region has the same impurity concentration as those of first low-concentration impurity regions, and thus can be formed in the same process as forming the first low-concentration impurity regions.
Claims
exact text as granted — not AI-modified1 - 20 . (canceled)
21 . A semiconductor device comprising:
a substrate including a MOS transistor region and a diode region; first and second impurity regions of a first conductivity type formed in the MOS transistor region; third and fourth impurity regions of the first conductivity type formed in the diode region; an interlayer insulating film formed over the MOS transistor region and the diode region; a first contact formed in the interlayer insulating film and electrically connected to the third impurity region; and a second contact formed in the interlayer insulating film and electrically connected to the fourth impurity region, wherein an impurity concentration of the first impurity region is higher than that of the second impurity region, wherein an impurity concentration of the third impurity region is higher than that of the fourth impurity region, wherein the third impurity region has the same impurity concentration as the first impurity region, wherein the fourth impurity region has the same impurity concentration as the second impurity region, and wherein the third impurity region is directly connected to the fourth impurity region.
22 . A semiconductor device according to claim 21 ,
wherein the first and second impurity regions serve as a source or a drain of a MOS transistor.
23 . A semiconductor device according to claim 21 , further comprising:
a first silicide layer formed on a surface of the first impurity region; and a second silicide layer formed on a surface layer of the third impurity region, wherein the first contact is connected to the second silicide layer.
24 . A semiconductor device according to the claim 23 ,
wherein the first silicide layer and the second silicide layer include the same metal.
25 . A semiconductor device according to the claim 23 , further comprising:
a third silicide layer formed on a part of a surface of the fourth impurity region, wherein the second contact is connected to the third silicide layer.Join the waitlist — get patent alerts
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