Memory architecture of thin film 3d array

Abstract

A 3D memory device includes an improved dual gate memory cell. The improved dual gate memory cell has a channel body with opposing first and second side surfaces, charge storage structures on the first and second side surfaces, and a gate structure overlying the charge storage structures on both the first and second side surfaces. The channel body has a depth between the first and second side surfaces less than a threshold channel body depth, combined with the gate structure which establishes an effective channel length of the cell greater than a threshold length. The combination of the channel body depth and effective channel length are related so that the cell channel body can be fully depleted, and sub-threshold leakage current can be suppressed when the memory cell has a high threshold state under a read bias.

What is claimed is: 
     
         1 . A device, comprising:
 a dual gate memory cell having a channel body with opposing first and second side surfaces, charge storage structures on the first and second side surfaces, and a gate structure overlying the charge storage structures on the first and second side surfaces, the channel body having a depth between the first and second side surfaces so that a channel body depth of the memory cell is less than a threshold channel body depth for fully depleted operation when the memory cell has a high threshold state under a read bias, and the gate structure having a width along the first and second side surfaces so that an effective channel length of the cell is greater than a threshold length to suppress sub-threshold leakage current when the memory cell has a high threshold state under the read bias.   
     
     
         2 . The device of  claim 1 , wherein the charge storage structures comprise memory elements that include dielectric charge trapping structures comprising a tunneling layer, a dielectric charge trapping layer and a blocking layer having in combination an equivalent oxide thickness, and where the gate structure width is more than the equivalent oxide thickness of the dielectric charge trapping structures. 
     
     
         3 . The device of  claim 1  wherein the memory cell comprises a dielectric charge trapping memory cell. 
     
     
         4 . The device of  claim 1 , wherein said threshold channel body depth is between 10 nm and 30 nm, and said threshold length is at least ⅔ the channel body depth. 
     
     
         5 . A device, comprising:
 a dual gate memory cell having a channel body with opposing first and second side surfaces, charge storage structures on the first and second side surfaces, and a gate structure overlying the charge storage structures on the first and second side surfaces, wherein the charge storage structure includes a dielectric charge trapping structure comprising a tunneling layer, a dielectric charge trapping layer and a blocking layer having in combination an equivalent oxide thickness, wherein the channel body has a depth between the first and second side surfaces so that a channel body depth of the memory cell is less than 40 nanometers, and the gate structure has a width along the first and second side surfaces so that an effective channel length of the cell is greater than ⅔ the effective oxide thickness and more than the channel body depth.   
     
     
         6 . The device of  claim 5  wherein the channel body depth of the memory cell is less than a threshold channel body depth for fully depleted operation when the memory cell has a high threshold state under a read bias, and the gate structure having a width along the first and second side surfaces so that an effective channel length of the cell is greater than a threshold length to suppress sub-threshold leakage current when the memory cell has a high threshold state under the read bias. 
     
     
         7 . A device, comprising:
 a plurality of stacks of semiconductor bit line strips including at least two semiconductor bit line strips separated by insulating material into different plane positions of a plurality of plane positions, the strips having opposing first and second side surfaces;   a plurality of word lines arranged orthogonally over, and having surfaces conformal with, the plurality of stacks, such that a 3D array of interface regions is established at cross-points between the first and second side surfaces of the strips in the plurality of stacks and the plurality of word lines; and   charge storage structures in the interface regions, which establish a 3D array of memory cells accessible via the plurality of semiconductor bit line strips and the plurality of word lines, the memory cells arranged in strings between bit line structures and source line structures, the charge storage structures including dielectric charge trapping structures comprising a tunneling layer, a dielectric charge trapping layer and a blocking layer having in combination an equivalent oxide thickness;   wherein the semiconductor bit line strips have depths between the first and second side surfaces so that channel body depths of the memory cells have depths between the first and second side surfaces so that a channel body depths of the memory cells are less than 40 nanometers, and the word lines have widths along the first and second side surfaces so that an effective channel length of the cell is greater than ⅔ the effective oxide thickness and more than the channel body depth.   
     
     
         8 . The device of  claim 7  wherein the channel body depths of the memory cells are less than a threshold channel body depth for fully depleted operation when the memory cells have a high threshold state under a read bias, and the gate structures having a width along the first and second side surfaces so that an effective channel length of the cells is greater than a threshold length to suppress sub-threshold leakage current when the memory cells have a high threshold state under the read bias. 
     
     
         9 . A memory device, comprising:
 an integrated circuit substrate; and   a 3D array of dual gate memory cells on the integrated circuit substrate, the 3D array including stacks of NAND strings of memory cells, the dual gate memory cells having channel body depths less than a threshold channel body depth for fully depleted operation when the corresponding memory cell has a high threshold state under a read bias, and effective channel lengths greater than a threshold length to suppress sub-threshold leakage current when the corresponding memory cell has a high threshold state under the read bias.   
     
     
         10 . The device of  claim 9 , wherein the memory cells comprise memory elements that include charge trapping structures comprising a tunneling layer, a dielectric charge trapping layer and a blocking layer. 
     
     
         11 . The device of  claim 9  wherein a channel body depth of the memory cells is less than 40 nanometers, and a gate structure has a width along first and second side surfaces of the memory cells so that the effective channel lengths of the cells are greater than ⅔ an effective oxide thickness of charge storage structures of the cells and more than the channel body depth.