Semiconductor Device Having Memory Cell With Electrostatic Capacitance Circuit

Abstract

A capacitance coupled to a memory node and a word line of an SRAM cell provides an electrostatic capacitance between the memory node and the word line. The capacitance has a first electrostatic capacitance when the word line is in a nonselective state (usually a LOW level) and the memory node retains a HIGH level; the capacitance has a second electrostatic capacitance which is smaller than the first electrostatic capacitance when the word line is in the nonselective state (usually the LOW level) and the memory node retains the LOW level.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a word line;   a pair of data lines; and   a memory cell coupled to the word line and the pair of data lines, the memory cell including:
 first and second memory nodes; 
 a flip-flop circuit to set one of the first and second memory nodes at a first potential and the other of the first and second memory nodes at a second potential which is lower than the first potential in response to stored data; 
 a first transfer transistor to control the connection between the first memory node and the first bit line in response to whether the word line is in a selective state or in a nonselective state; 
 a second transfer transistor to control the connection between the second memory node and the second bit line in response to whether the word line is in the selective state or in the nonselective state; 
 a first capacitive element coupled between the first memory node and the word line; 
 a second capacitive element coupled between the second memory node and the word line; 
 a third wiring functioning as a gate electrode for both the first transfer transistor and the first capacitive element; and 
 a fourth wiring functioning as a gate electrode for both the second transfer transistor and the second capacitive element. 
   
     
     
         2 . A semiconductor device according to  claim 1 ,
 wherein in a plan view layout of the memory cell:   the third and fourth wirings extend in a common first direction of the memory cell and are parallel to one another but do not overlap in a second direction which is orthogonal to the first direction.   
     
     
         3 . A semiconductor device according to  claim 1 ,
 wherein the flip-flop circuit comprises:   a first PMOS transistor and a first NMOS transistor coupled to each other in series between a high reference voltage and a low reference voltage, wherein gates of the first PMOS transistor and the first NMOS transistor are coupled to the second memory node and drains of the first PMOS transistor and the first NMOS transistor are coupled to the first memory node, and   a second PMOS transistor and a second NMOS transistor coupled to each other in series between the high reference voltage and the low reference voltage, wherein gates of the second PMOS transistor and the second NMOS transistor are coupled to the first memory node and drains of the second PMOS transistor and the second NMOS transistor are coupled to the second memory node; and   a first wiring functioning as a gate electrode for both the first PMOS transistor and the first NMOS transistor; and   a second wiring functioning as a gate electrode for both the second PMOS transistor and the second NMOS transistor.   
     
     
         4 . A semiconductor device according to  claim 3 ,
 wherein in a plan view layout of the memory cell:   the first and second wirings extend in a common first direction of the memory cell and are parallel to one another but do not overlap in a second direction which is orthogonal to the first direction;   the third and fourth wirings extend in the common first direction of said each memory cell and are parallel to one another but do not overlap in the second direction;   the first and fourth wirings are collinear; and   the second and third polysilicon wirings are collinear.   
     
     
         5 . A semiconductor device according to  claim 1 ,
 wherein the first capacitive element has a first electrostatic capacitance when the word line is in the nonselective state and the first memory node has the first potential, and has a second electrostatic capacitance which is smaller than the first electrostatic capacitance when the word line is in the nonselective state and the first memory node has the second potential, and   wherein the second capacitive element has a third electrostatic capacitance when the word line is in the nonselective state and the second memory node has the first potential, and has a fourth electrostatic capacitance which is smaller than the third electrostatic capacitance when the word line is in the nonselective state and the second memory node has the second potential.   
     
     
         6 . A semiconductor device comprising:
 a CPU;   a static random access memory coupled to the CPU, the memory including:
 a word line; 
 a pair of data lines; and 
 a memory cell coupled to the word line and the pair of data lines, 
   wherein the memory cell includes:
 first and second memory nodes; 
 a flip-flop circuit to set one of the first and second memory nodes at a first potential and the other of the first and second memory nodes at a second potential which is lower than the first potential in response to stored data; 
 a first transfer transistor to control the connection between the first memory node and the first bit line in response to whether the word line is in a selective state or in a nonselective state; 
 a second transfer transistor to control the connection between the second memory node and the second bit line in response to whether the word line is in the selective state or in the nonselective state; 
 a first capacitive element coupled between the first memory node and the word line; 
 a second capacitive element coupled between the second memory node and the word line; 
 a third wiring functioning as a gate electrode for both the first transfer transistor and the first capacitive element; and 
 a fourth wiring functioning as a gate electrode for both the second transfer transistor and the second capacitive element. 
   
     
     
         7 . A semiconductor device according to  claim 6 ,
 wherein in a plan view layout of the memory cell:   the third and fourth wirings extend in a common first direction of the memory cell and are parallel to one another but do not overlap in a second direction which is orthogonal to the first direction.   
     
     
         8 . A semiconductor device according to  claim 6 ,
 wherein the flip-flop circuit comprises:   a first PMOS transistor and a first NMOS transistor coupled to each other in series between a high reference voltage and a low reference voltage, wherein gates of the first PMOS transistor and the first NMOS transistor are coupled to the second memory node and drains of the first PMOS transistor and the first NMOS transistor are coupled to the first memory node, and   a second PMOS transistor and a second NMOS transistor coupled to each other in series between the high reference voltage and the low reference voltage, wherein gates of the second PMOS transistor and the second NMOS transistor are coupled to the first memory node and drains of the second PMOS transistor and the second NMOS transistor are coupled to the second memory node; and   a first wiring functioning as a gate electrode for both the first PMOS transistor and the first NMOS transistor; and   a second wiring functioning as a gate electrode for both the second PMOS transistor and the second NMOS transistor.   
     
     
         9 . A semiconductor device according to  claim 8 ,
 wherein in a plan view layout of the memory cell:   the first and second wirings extend in a common first direction of the memory cell and are parallel to one another but do not overlap in a second direction which is orthogonal to the first direction;   the third and fourth wirings extend in the common first direction of said each memory cell and are parallel to one another but do not overlap in the second direction;   the first and fourth wirings are collinear; and   the second and third polysilicon wirings are collinear.   
     
     
         10 . A semiconductor device according to  claim 6 ,
 wherein the first capacitive element has a first electrostatic capacitance when the word line is in the nonselective state and the first memory node has the first potential, and has a second electrostatic capacitance which is smaller than the first electrostatic capacitance when the word line is in the nonselective state and the first memory node has the second potential, and   wherein the second capacitive element has a third electrostatic capacitance when the word line is in the nonselective state and the second memory node has the first potential, and has a fourth electrostatic capacitance which is smaller than the third electrostatic capacitance when the word line is in the nonselective state and the second memory node has the second potential.